Refresh control circuit and method for semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorYoung-Bo Shim
Life of this patent
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Abstract
A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.
Claims18
A refresh control circuit for a semiconductor memory device, comprising:
- a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, a mode determination signal having refresh mode information, and an active signal enabled in an active mode;
- a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to the active signal;
- and
- a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.
A method for controlling a refresh operation of a semiconductor memory device, comprising:
- determining the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, a mode determination signal having refresh mode information, and an active signal enabled in an active mode;
- outputting a row address for a refresh operation by counting the refresh signal in response to the active signal;
- and
- generating a row address selection signal for sequentially accessing word lines within a cell array by decoding the row address.
Dependencies are inferred from the claim text.