US 8,284,614 B2 · Refresh control circuit and method for semiconductor memory device

Abstract

A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode selection signal enabled in an external address refresh mode, an address selector for outputting the refresh address from the refresh counter as a selection row address in a normal refresh mode and outputting the internal address from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal, and a row address decoder for generating a row address selection signal for sequentially accessing word lines by decoding the selection row address.

Claims16

Dependent claims

A semiconductor memory device comprising:

a refresh counter configured to count a refresh signal and output a refresh address in response to an active mode signal enabled in an active mode;
an external address input buffer configured to buffer an external address and output an internal address in response to a mode selection signal enabled in an external address refresh mode;
an address selector configured to output the refresh address transferred from the refresh counter as a selection row address in a normal refresh mode and output the internal address transferred from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal;
and
a row address decoder configured to generate a row address selection signal for sequentially accessing word lines in a cell array by decoding the selection row address.

2 more elements

A method for controlling a refresh operation in a semiconductor memory device, comprising:

counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode;
buffering an external address and outputting an internal address in response to a mode selection signal enabled in an external address refresh mode;
outputting the refresh address as a selection row address in a normal refresh mode and outputting the internal address as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal;
and
generating a row address selection signal for sequentially accessing word lines in a cell array by decoding the selection row address.

2 more elements

Dependencies are inferred from the claim text.

Refresh control circuit and method for semiconductor memory device

Life of this patent

Refresh control circuit and method for semiconductor memory device

Life of this patent

Abstract

Claims16