Verifying and programming method of nonvolatile memory device
AssigneeHynix Semiconductor Inc.
InventorEun Joung Lee
Life of this patent
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Abstract
A method of operating a nonvolatile memory device includes precharging bit lines coupled to strings, supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line, supplying a first sense pulse to switching elements coupled between the bit lines and sense nodes and detecting memory cells, each having a threshold voltage higher than the first verification voltage, supplying a second verification voltage higher than the first verification voltage to the selected word line and supplying the pass voltage to the word lines other than the selected word line, and supplying a second sense pulse to the switching elements and detecting memory cells, each having a threshold voltage higher than the second verification voltage.
Claims15
A verifying method of a nonvolatile memory device, the method comprising:
- precharging bit lines coupled to strings;
- supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line;
- supplying a first sense pulse to switching elements coupled between the bit lines and sense nodes and detecting memory cells, each having a threshold voltage higher than the first verification voltage;
- supplying a second verification voltage higher than the first verification voltage to the selected word line and supplying the pass voltage to the word lines other than the selected word line;
- and
- supplying a second sense pulse to the switching elements and detecting memory cells, each having a threshold voltage higher than the second verification voltage, wherein a voltage level of the second sense pulse is lower than a voltage level of the first sense pulse.
A programming method of a nonvolatile memory device comprising a plurality of strings, bit lines coupled to the respective strings, and switching elements coupled between a sense node and the respective bit lines, the method comprising:
- programming selected memory cells of the string;
- precharging the bit lines;
- supplying a first verification voltage to a selected word line coupled to the selected memory cells, supplying a first sense pulse to the switching elements, and detecting memory cells, each having a threshold voltage higher than the first verification voltage, by sensing an amount of charges transferred to the sense node;
- supplying a second verification voltage higher than the first verification voltage to the selected word line, supplying a second sense pulse to the switching element, and detecting memory cells, each having a threshold voltage higher than the second verification voltage, by sensing an amount of charges transferred to the sense node;
- and
- supplying a third verification voltage higher than the second verification voltage to the selected word line, supplying a third sense pulse to the switching element, and detecting memory cells, each having a threshold voltage higher than the third verification voltage, by detecting an amount of charges transferred to the sense nod,
- wherein the first to third sense pulses are set to be gradually lowered.
A verifying method of a nonvolatile memory device, the method comprising:
- precharging bit lines coupled to strings;
- supplying a first verification voltage to a selected word line of the strings;
- sensing the bit lines in response to a first sense pulse to verify a memory cell of the selected word line is programmed in a first state;
- supplying a second verification voltage higher than the first verification voltage to the selected word line;
- and
- sensing the bit lines in response to a second sense pulse to verify the memory cell of the selected word line is programmed in a second state, wherein the second sense pulse is lower than the first sense pulse.
Dependencies are inferred from the claim text.