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US 8,284,607 B2Granted
Semiconductor memory system including a plurality of semiconductor memory devices
AssigneeKabushiki Kaisha Toshiba
InventorsNoboru Shibata, Hiroshi Sukegawa
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Abstract
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
Claims5
A semiconductor memory system comprising:
- a first semiconductor memory device;
- a second semiconductor memory device;
- a controller connected to the first and second semiconductor memory devices;
- and
- a voltage generation circuit provided in the controller, and generating a voltage, the controller supplying a voltage generated by the voltage generation circuit to one of the first and second semiconductor memory devices,
- wherein the controller supplies the voltage to one of the first and second semiconductor memory devices without overlapping a peak current of the first and second semiconductor memory devices.
3 more elements
Dependencies are inferred from the claim text.