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US 8,284,604 B2Granted
NOR flash memory device and related methods of operation
AssigneeSamsung Electronics Co., Ltd.
InventorJi ho Cho
Life of this patent
Estimating the term…
Abstract
A NOR flash memory device is programmed by selecting one of a plurality of global bit lines and sequentially selecting a plurality of local bit lines commonly connected with the selected global bit line to supply a program voltage to memory cells.
Claims12
A method of operating a NOR flash memory device, comprising:
- selecting one of a plurality of global bit lines;
- selecting a plurality of local bit lines commonly connected with the selected global bit line in a predetermined sequence to supply a program voltage to memory cells of the NOR flash memory device;
- selecting another one of the plurality of global bit lines;
- and
- selecting another plurality of local bit lines commonly connected with the another one of the plurality of global bit lines in a predetermined sequence to supply the program voltage to additional memory cells of the NOR flash memory device,
- wherein the another one of the plurality of global bit lines is identified for selection by incrementing an index within a controller.
3 more elements
A method of erasing a NOR flash memory device, comprising:
- performing an erase operation;
- and
- performing a program operation before or after the erase operation,
- wherein the program operation comprises:
- selecting one of a plurality of global bit lines, and selecting a plurality of local bit lines commonly connected with the selected global bit line in a predetermined sequence to supply a program voltage to memory cells of the NOR flash memory device;
- and
- selecting another one of the plurality of global bit lines;
- and selecting another plurality of local bit lines commonly connected with the another one of the plurality of global bit lines in a predetermined sequence to supply the program voltage to additional memory cells of the NOR flash memory device,
- wherein the another one of the plurality of global bit lines is identified for selection by incrementing an index within a controller.
6 more elements
A NOR flash memory device comprising:
- a memory cell array comprising local bit lines and global bit lines;
- a bit line selection circuit configured to select the local bit lines and the global bit lines in response to local and global bit line selection signals;
- and
- a decoder configured to generate the local and global bit line selection signals to select local bit lines in a predetermined sequence during an activation of a global bit line in a pre-program or post-program operation,
- wherein the decoder comprises:
- a first bit line decoder configured to generate the global and local bit line selection signals such that one of the global bit lines is selected and local bit lines connected with the selected global bit line are selected sequentially;
- a second bit line decoder configured to generate the global and local bit line selection signals such that one of local bit lines is selected and a global bit line corresponding to the selected local bit line is selected;
- and
- a selection circuit configured to select one of the first bit line decoder and the second bit line decoder.
6 more elements
Dependencies are inferred from the claim text.