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US 8,284,598 B2Granted
Semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorsHiroyuki Takahashi, Naoki Ookuma
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes: a memory cell array provided with a plurality of memory cells in a matrix; and a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of the plurality of memory cells.
Claims8
A semiconductor memory device comprising:
- a memory cell array provided with a plurality of memory cells in a matrix;
- and
- a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of said plurality of memory cells,
- wherein said power supply circuit comprises:
- a first intermediate voltage generating circuit configured to generate a first intermediate voltage between said power supply voltage and said ground voltage;
- a second intermediate voltage generating circuit configured to generate a second intermediate voltage between said power supply voltage and said ground voltage;
- a first output node to which said first intermediate voltage is supplied;
- a second output node to which said second intermediate voltage is supplied;
- and
- a connection control circuit provided between said first output node and said second output node,
- wherein said first intermediate voltage generating circuit supplies said first intermediate voltage in response to a first control signal, and said second intermediate voltage generating circuit stops its operation in response to said first control signal, and
- wherein said connection control circuit connects said first output node and said second output node when said second intermediate voltage generating circuit stops its operation.
9 more elements
A semiconductor memory device comprising:
- a memory cell;
- and
- a power supply circuit configured to supply to said memory cell a predetermined voltage between a first power supply voltage and a second power supply voltage which is lower than said first power supply voltage,
- wherein said power supply circuit comprises:
- first and second output nodes;
- first and second intermediate voltage generating circuits connected with said first and second output nodes, respectively;
- and
- a connection control circuit provided between said first and second output nodes,
- wherein said predetermined voltage is supplied to said first and second output nodes by using both of said first and second intermediate voltage generating circuits or only said first intermediate voltage generating circuit based on a combination of an active state of said connection control circuit, and active states of said first and second intermediate voltage generating circuits.
6 more elements
Dependencies are inferred from the claim text.