Back to results
US 8,284,592 B2Granted
Semiconductor memory device and method of updating data stored in the semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKeiichi Kushida
Life of this patent
Estimating the term…
Abstract
The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.
Claims19
A semiconductor memory device comprising:
- a memory cell array comprising memory cells in a matrix arrangement;
- a data inverter configured to invert data in the memory cells and to write the inverted data in the memory cells;
- an address counter configured to increment or decrement an internal address when the data inverter writes the inverted data;
- a decoder configured to select a first memory cell comprising data to be inverted by the data inverter based on the internal address designated by the address counter;
- and
- an address comparator configured to determine whether the data from a memory cell of an external address is inverted and written based on a first result of comparison of an external address and the internal address in a readout cycle, and to determine whether the data written into a memory cell of the external address is inverted based on a second result of comparison of the external address and the internal address in a writing cycle.
3 more elements
A semiconductor memory device comprising:
- a memory cell array comprising memory cells in a matrix arrangement;
- a row decoder configured to select a memory cell to be accessed in a row direction;
- a column decoder configured to select a memory cell to be accessed in a column direction;
- a sense amplifier configured to amplify a signal from the memory cell in order to detect whether data in the memory cell is a logical value 0 or a logical value 1;
- a word line configured to transmit a signal exchanged between the row decoder and the memory cell;
- a bit line configured to transmit a signal exchanged between the sense amplifier and the memory cell;
- an address counter configured to generate an internal address;
- an address comparator configured to compare the internal address from the address counter and an external address from the outside and to determine whether an inverted region is designated or a non-inverted region is designated by the external address;
- an NOP controller configured to cause the semiconductor memory device to read data from the memory cell, invert the read-out data, and to write the data in the memory cell during a standby cycle;
- a register configured to store the data detected by the sense amplifier;
- a first inverter configured to invert the data in the register;
- a second inverter configured to invert written data;
- a first selector configured to select a detection value of a signal of a first bit line of a complementary pair, based on a result of the comparison of the address comparator;
- a second selector configured to select the written data or the inverted written data based on the result of the comparison of the address comparator;
- a third selector configured to select either the data selected by the second selector or the data inverted by the first inverter based on a command from the NOP controller;
- and
- a data latch and write controller configured to set potential of the first bit line either to a high level or to a low level according to the data selected by the third selector.
14 more elements
A method of updating data in a semiconductor memory device, the method comprising:
- reading data in memory cells in a matrix arrangement in a memory cell array in a standby cycle, inverting the read data, and writing the read data in the memory cells;
- determining whether a region designated by an external address in a readout cycle is an inverted region or a non-inverted region;
- outputting data after inverting the read data in the readout cycle when the region designated by the external address is the inverted region;
- outputting the read data in the readout cycle without inversion when the region designated by the external address is the non-inverted region;
- determining whether a region designated by an external address in a writing cycle is the inverted region or the non-inverted region;
- writing data after inverting written data in the memory cells in the writing cycle when the region designated by the external address is the inverted region;
- and
- writing the written data in the memory cells without inversion in the writing cycle when the region designated by the external address is the non-inverted region.
5 more elements
Dependencies are inferred from the claim text.