Semiconductor memory device and test method therefor

#This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-045330, filed on Feb. 27, 2009, the disclosure of which is incorporated herein in its entirety by reference.

#1. Field of the Invention

#The present invention relates to a semiconductor memory device and a test method therefor, and more particularly, to a static random access memory (SRAM) and a test method therefor.

#The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a circuit diagram illustrating a semiconductor memory device according to a first exemplary embodiment of the present invention;

#FIG. 2 is a detailed circuit diagram illustrating a part of the semiconductor memory device shown in FIG. 1;

#Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to exemplary embodiments described below. The following descriptions and drawings are simplified as appropriate to clarify the explanation.

#FIG. 1 is a circuit diagram illustrating a semiconductor memory device according to a first exemplary embodiment of the present invention. The semiconductor memory device is an SRAM. The semiconductor memory device includes a control circuit CTR, a sense amplifier SA, a write circuit WC, n (n is a natural number) pairs of Y selectors YS1a to YSna and YS1b to YSnb, n pairs of precharge circuits PC1a to PCna and PC1b to PCnb, 2n pairs of bit lines BLT1a and BLB1a to BLTna and BLBna, and BLT1b and BLB1b to BLTnb and BLBnb, a pair of word line selectors WLSa and WLSb, m (m is a natural number) pairs of word lines WL1a to WLma and WL1b to WLmb, and n×m pairs of memory cells MC. The sense amplifier and write circuit SA/WC includes the sense amplifier SA and the write circuit WC which are integrally illustrated in FIG. 1 for convenience of illustration. The sense amplifier SA is a circuit that amplifies a potential difference between two sense nodes of a memory cell MC selected in a read operation. In the case of a memory cell MC1, for example, the sense nodes herein described refer to nodes at which the memory cell MC1 is connected with the bit line pair BLT1a and BLB1a. The write circuit WC is a circuit that writes data to the selected memory cell MC in a write operation. That is, the sense amplifier SA and the write circuit WC complementarily operate at different timings.

#The sense amplifier and write circuit SA/WC is connected with the n pairs of Y selectors YS1a to YSna and YS1b to YSnb. Each of the Y selectors is connected with a bit line pair including two bit lines. For example, the Y selector YS1a is connected with the bit line pair BLT1a and BLB1a.