Semiconductor memory with sense amplifier and driver transistor rows

A semiconductor memory device comprising:

• a sense-amplifier row arranged in a first direction;
• a driver-transistor row that supplies a voltage to the sense-amplifier row, the driver-transistor row being arranged in parallel with the first direction and comprised of plural alternating first conductive type well regions of second conductive type driver transistors and second conductive type well regions of first conductive type driver transistors such that each first conductive type well region is located in line with and adjacently between two second conductive type well regions;
• and
• an element separation region continuously extending from the first direction so as to cross the driver transistor row in a direction intersecting the first direction, the element separation region defining a boundary line separating the adjacent first and second conductive type well regions.

A semiconductor memory device, comprising:

• sense amplifiers driving bit lines to which memory cells are connected, the sense amplifiers having i) a first transistor region in which transistors of a first conductive type are arranged, and ii) a second transistor region in which transistors of a second conductive type are arranged,
• the first transistor region extending in a first direction in parallel with the second transistor region;
• driver transistors supplying a power supply to the sense amplifiers, the driver transistors having i) a first driver transistor region in which at least one transistor of the first conductive type are arranged between the first and second transistor regions, and ii) a second driver transistor region in which at least one transistor of the second conductive type are arranged between the first and second transistor regions,
• the first driver transistor region having a first point,
• the second driver transistor region having a second point,
• the first and second points aligned on a straight line parallel to the first direction.