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US 8,284,561 B2Granted
Embedded component package structure
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsYuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt, Ming-Chiang Lee
Life of this patent
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Abstract
The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.
Claims19
A package structure, comprising:
- a first laminate structure having a first double-layered sheet and a first metal layer disposed below the first double-layered sheet, wherein the first double-layered sheet consists of a first dielectric layer and a second metal layer, the first and second metal layers are separated by the first dielectric layer and the first dielectric layer is sandwiched between the first and second metal layers;
- a second laminate structure having at least a cavity therein, wherein the second laminate structure consists of a third metal layer and a second dielectric layer disposed on the third metal layer;
- an interlayer joining the first laminate structure and the second laminate structure, wherein the first metal layer is joined to a surface of the interlayer and the second dielectric layer of the second laminate structure is joined to the opposite surface of the interlayer;
- a plurality of bonding pads, located within the at least cavity and on the first metal layer;
- a plurality of plated-through hole structures, extending through the first laminate structure, the interlayer and the second laminate structure;
- at least an electronic component, electrically connected to and mounted on the plurality of the bonding pads;
- and
- an encapsulant, filling up the at least cavity and encapsulating the at least electronic component.
5 more elements
A package structure, comprising:
- a first laminate structure having a first dielectric layer and a first metal layer disposed below the first dielectric layer;
- a second laminate structure having at least a cavity therein, wherein the second laminate structure consists of a second metal layer and a second dielectric layer disposed on the second metal layer;
- an interlayer joining the first laminate structure and the second laminate structure, wherein the first metal layer is joined to a surface of the interlayer and the second dielectric layer of the second laminate structure is joined to the opposite surface of the interlayer;
- a plurality of bonding pads, located within the at least cavity and on the first metal layer, wherein the at least cavity exposes a portion of the interlayer and the plurality of bonding pads;
- a plurality of plated-through hole structures, extending through the first laminate structure, the interlayer and the second laminate structure;
- a top solder resist coating covering a top surface of the first dielectric layer and the plurality of plated-through hole structures;
- a bottom solder resist coating over the plurality of plated-through hole structures and the second laminate structure;
- at least an electronic component, electrically connected to and mounted on the plurality of the bonding pads;
- and
- an encapsulant, filling up the at least cavity and encapsulating the at least electronic component.
7 more elements
Dependencies are inferred from the claim text.