US 8,284,183 B2Granted

Inverter circuit and display device

AssigneeSony Corporation

InventorsTetsuro Yamamoto, Katsuhide Uchino

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Abstract

An inverter circuit including: first to third transistors; first and second switches; and a first capacitive element. The first and second transistors are connected in series between a first voltage line and a second voltage line. The third transistor is connected between the second voltage line and a gate of the second transistor. The first and second switches are connected in series between a voltage supply line and a gate of the third transistor, and are turned on/off alternately to prevent the first and second switches from simultaneously turning ON. One end of the first capacitive element is connected to a node between the first and second switches. Off-state of the first transistor allows a predetermined fixed voltage to be supplied from the voltage supply line to the gate of the second transistor, via the first switch, the one end of the first capacitive element and the second switch.

Claims13

Dependent claims

An inverter circuit comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type;
a first capacitive element;
and
an input terminal and an output terminal,
wherein the first transistor makes or breaks electric connection between the output terminal and a first voltage line, in response to a potential difference between a voltage of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto,
the second transistor makes or breaks electric connection between a second voltage line and the output terminal, in response to a potential difference between a voltage of a first terminal that is a source or a drain of the seventh transistor and a voltage of the output terminal or a potential difference corresponding thereto,
the third transistor makes or breaks electric connection between a gate of the seventh transistor and the third voltage line, in response to a potential difference between the voltage of the input terminal and a voltage of a third voltage line or a potential difference corresponding thereto,
the fourth transistor makes or breaks electric connection between the first capacitive element and the gate of the seventh transistor, in response to a first control signal inputted into a gate of the fourth transistor,
the fifth transistor makes or breaks electric connection between the first capacitive element and a fourth voltage line, in response to a second control signal inputted into a gate of the fifth transistor,
the sixth transistor makes or breaks electric connection between the first terminal and the fifth voltage line, in response to a potential difference between the voltage of the input terminal and a voltage of a fifth voltage line or a potential difference corresponding thereto,
the seventh transistor makes or breaks electric connection between the first terminal and a sixth voltage line, in response to a potential difference between a gate voltage of the seventh transistor and a gate voltage of the second transistor or a potential difference corresponding thereto, and
the first capacitive element is inserted between a drain or a source of the fifth transistor and a seventh voltage line.

9 more elements

An inverter circuit comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type;
a first capacitive element;
and
an input terminal and an output terminal,
wherein a gate of the first transistor is electrically connected to the input terminal, one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal,
one terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal,
a gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the seventh transistor,
a gate of the fourth transistor is supplied with a first control signal, and one terminal of a drain and a source of the fourth transistor is electrically connected to the gate of the seventh transistor,
a gate of the fifth transistor is supplied with a second control signal, one terminal of a drain and a source of the fifth transistor is electrically connected to a fourth voltage line, and the other terminal of the fifth transistor is electrically connected to the other terminal of the fourth transistor,
a gate of the sixth transistor is electrically connected to the input terminal, one terminal of a drain and a source of the sixth transistor is electrically connected to a fifth voltage line, and the other terminal of the sixth transistor is electrically connected to the gate of the second transistor,
one terminal of a drain and a source of the seventh transistor is electrically connected to a sixth voltage line, and the other terminal of the seventh transistor is electrically connected to the gate of the second transistor, and
the first capacitive element is inserted between the other terminal of the fifth transistor and a seventh voltage line.

9 more elements

A display device having a display section and a drive section, the display section including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns and a plurality of pixels arranged in rows and columns, and the drive section including a plurality of inverter circuits each provided for each of the scanning lines to drive each of the pixels, each of the inverter circuits comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type;
a first capacitive element;
and
an input terminal and an output terminal,
wherein the first transistor makes or breaks electric connection between the output terminal and a first voltage line, in response to a potential difference between a voltage of the input terminal and a voltage of the first voltage line or a potential difference corresponding thereto,
the second transistor makes or breaks electric connection between a second voltage line and the output terminal, in response to a potential difference between a voltage of a first terminal that is a source or a drain of the seventh transistor and a voltage of the output terminal or a potential difference corresponding thereto,
the third transistor makes or breaks electric connection between a gate of the seventh transistor and the third voltage line, in response to a potential difference between the voltage of the input terminal and a voltage of a third voltage line or a potential difference corresponding thereto,
the fourth transistor makes or breaks electric connection between the first capacitive element and the gate of the seventh transistor, in response to a first control signal inputted into a gate of the fourth transistor,
the fifth transistor makes or breaks electric connection between the first capacitive element and a fourth voltage line, in response to a second control signal inputted into a gate of the fifth transistor,
the sixth transistor makes or breaks electric connection between the first terminal and the fifth voltage line, in response to a potential difference between the voltage of the input terminal and a voltage of a fifth voltage line or a potential difference corresponding thereto,
the seventh transistor makes or breaks electric connection between the first terminal and a sixth voltage line, in response to a potential difference between a gate voltage of the seventh transistor and a gate voltage of the second transistor or a potential difference corresponding thereto, and
the first capacitive element is inserted between a drain or a source of the fifth transistor and a seventh voltage line.

9 more elements

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor each having channels of same conduction type;
a first capacitive element;
and
an input terminal and an output terminal,
wherein a gate of the first transistor is electrically connected to the input terminal, one terminal of a drain and a source of the first transistor is electrically connected to a first voltage line, and the other terminal of the first transistor is electrically connected to the output terminal,
one terminal of a drain and a source of the second transistor is electrically connected to a second voltage line, and the other terminal of the second transistor is electrically connected to the output terminal,
a gate of the third transistor is electrically connected to the input terminal, one terminal of a drain and a source of the third transistor is electrically connected to a third voltage line, and the other terminal of the third transistor is electrically connected to a gate of the seventh transistor,
a gate of the fourth transistor is supplied with a first control signal, and one terminal of a drain and a source of the fourth transistor is electrically connected to the gate of the seventh transistor,
a gate of the fifth transistor is supplied with a second control signal, one terminal of a drain and a source of the fifth transistor is electrically connected to a fourth voltage line, and the other terminal of the fifth transistor is electrically connected to the other terminal of the fourth transistor,
a gate of the sixth transistor is electrically connected to the input terminal, one terminal of a drain and a source of the sixth transistor is electrically connected to a fifth voltage line, and the other terminal of the sixth transistor is electrically connected to the gate of the second transistor,
one terminal of a drain and a source of the seventh transistor is electrically connected to a sixth voltage line, and the other terminal of the seventh transistor is electrically connected to the gate of the second transistor, and
the first capacitive element is inserted between the other terminal of the fifth transistor and a seventh voltage line.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/064,220Filed 11 Mar 2011
Priority: JP 2010-0854921 Apr 2010
Published: US 2011/0242069 A16 Oct 2011
Granted: 9 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G09G 3/3266
Organic, e.g. using organic light-emitting diodes [OLED]: details of drivers for scan electrodes
G09G 3/3233
Using an active matrix: with pixel circuitry controlling the current through the light-emitting element
G09G 2300/0819
Several active elements per pixel in active matrix panels: used for counteracting undesired variations, e.g. feedback or autozeroing
G09G 2300/0842
Several active elements per pixel in active matrix panels: forming a memory circuit, e.g. a dynamic memory with one capacitor