Method and system for reduced clock feed-through in a phase locked loop

A system for signal processing, the system comprising:

• one or more circuits that are operable to generate a control voltage for a voltage controlled oscillator, said one or more circuits comprising a filter, a first transmission gate, a second transmission gate that is operable to reset at least a portion of said filter, and at least one clock booster circuit, wherein:
• a first of said at least one clock booster circuit is operable to clock said first transmission gate;
• and
• said filter comprises one or more thick oxide transistors to reduce clock feed-through.

A method for signal processing, the method comprising:

• generating, via a filter, a control voltage for controlling a voltage controlled oscillator, wherein:
• said filter comprises at least one switching element clocked via a clock booster circuit;
• said filter comprises one or more thick oxide transistors to reduce clock feed-through;
• a first switching element of said filter is a first transmission gate comprising an N-type thick oxide transistor and a P-type thick oxide transistor;
• said first transmission gate is part of a sample and hold circuit, where a first terminal of said first transmission gate is communicatively coupled to a first capacitor and a second terminal of said first transmission gate is communicatively coupled to a second capacitor;
• periodically resetting a DC voltage on an input node of said sample and hold circuit via a reset switching element, wherein said reset switching element is a second transmission gate comprising an N-type thick oxide transistor and a P-type thick oxide transistor;
• and
• controlling said voltage controlled oscillator utilizing said generated control voltage.

A system for signal processing, the system comprising:

• one or more circuits for generating a control voltage for a voltage controlled oscillator, said one or more circuits comprising a filter, at least one switching element, and at least one clock booster circuit, wherein:
• a first of said at least one clock booster circuit is operable to clock said at least one switching element;
• said filter comprises one or more thick oxide transistors to reduce clock feed-through;
• a first switching element of said filter is a first transmission gate comprising an N-type thick oxide transistor and a P-type thick oxide transistor;
• said one or more circuits comprise a sample and hold circuit and said first transmission gate is part of said sample and hold circuit;
• a first terminal of said first transmission gate is communicatively coupled to a first capacitor and a second terminal of said first transmission gate is communicatively coupled to a second capacitor;
• said one or more circuits comprise a reset switching element, and said reset switching element is operable to periodically reset a DC voltage on an input node of said sample and hold circuit;
• and
• said reset switching element is a second transmission gate comprising an N-type thick oxide transistor and a P-type thick oxide transistor.