Method and apparatus of phase locking for reducing clock jitter due to charge leakage
AssigneeReal Tek Semiconductor Corp.
InventorChia-Liang Lin
Life of this patent
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Abstract
A phase lock loop is disclosed comprising a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal.
Claims19
An apparatus for generating an output clock, comprising:
- a first phase detector configured to receive a first clock and a second clock and output a first detector output signal;
- a second phase detector configured to receive the first clock and the second clock and output a second detector output signal, wherein the first phase detector has a first charge leakage and the second phase detector has a second charge leakage, the first charge leakage is larger than the second charge leakage;
- a summing circuit to sum the first detector output signal and the second detector output signal into a control signal;
- a loop filter to filter the control signal into a refined control signal;
- and
- a controllable oscillator to generate the output clock in accordance with a control by the refined control signal;
- wherein the second clock corresponds to the output clock.
A method of phase locking, the method comprising:
- receiving a first clock and a second clock;
- generating a first phase detector output signal to represent a timing difference between the first clock and the second clock using a primary phase detector;
- generating a second phase detector output signal to represent the timing difference between the first clock and the second clock using a secondary phase detector;
- summing the first detector output signal and the second phase detector output signal into a control signal;
- and
- filtering the control signal into a refined control signal;
- generating an output clock in accordance with a frequency controlled by the refined control signal, wherein the second clock corresponds to the output clock;
- wherein the step of generating the second detector output signal is disabled during a first phase and enabled during a second phase.
An apparatus for generating an output clock, comprising:
- a first phase detector configured to receive a first clock and a second clock and output a first detector output signal, wherein the second clock corresponds to the output clock;
- a second phase detector configured to receive the first clock and the second clock and output a second detector output signal;
- a summing circuit to sum the first detector output signal and the second detector output signal into a control signal;
- a loop filter to filter the control signal into a refined control signal;
- and
- a controllable oscillator to generate the output clock in accordance with a control by the refined control signal;
- wherein the first phase detector comprises a hiqh-speed device and the second phase detector comprises a low-speed device.
Dependencies are inferred from the claim text.