US 8,283,964 B2Granted

Level shifters and high voltage logic circuits

AssigneeQUALCOMM Incorporated

InventorMarco Cassia

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Abstract

Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.

Claims15

Dependent claims

An apparatus comprising:

a driver circuit including:
a first and a second inverter and configured to receive a first and a second input signal of a differential input signal comprising Vinp and Vinn signals having a first voltage range at the first and second inverters, respectively, and provide a differential drive signal comprising Vdrp and Vdrn signals having a second voltage range different from the first voltage range;
the first inverter to receive the Vinp signal and provide a first intermediate signal,
a third inverter coupled to the first inverter and to receive the first intermediate signal and provide a first control signal,
a first metal oxide semiconductor (MOS) transistor coupled to the third inverter and to receive the first control signal and provide the Vdrp signal,
the second inverter to receive the Vinn signal and provide a second intermediate signal,
a fourth inverter coupled to the second inverter and to receive the second intermediate signal and provide a second control signal, and
a second MOS transistor coupled to the fourth inverter and to receive the second control signal and provide the Vdrn signal;
and
a latch coupled to the driver circuit and to receive the differential drive signal and provide an output signal having the second voltage range.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/633,675Filed 8 Dec 2009 · us provisional application
Priority: 22 Jul 2009
Published: US 2011/0018606 A127 Jan 2011
Granted: 9 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H03K 3/35613
Using additional transistors in the input circuit: the input circuit having a differential configuration
H03K 19/018528
Of complementary type, e.g. CMOS: with at least one differential stage
H03K
Pulse technique