Back to results
US 8,283,962 B2Granted
Semiconductor device and operation method thereof for generating phase clock signals
AssigneeHynix Semiconductor Inc.
InventorsDae-Han Kwon, Kyung-Hoon Kim, Dae-Kun Yoon, Taek-Sang Song
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.
Claims21
A semiconductor device comprising:
- a reset signal generating unit configured to generate a plurality of reset signals in response to a control signal, wherein the plurality of the reset signals have different activation timings according to a constant phase difference;
- and
- a multi-phase clock signal generating unit configured to divide a frequency of a source clock signal in response to the plurality of the reset signals in order to generate a plurality of phase clock signals having the constant phase difference,
- wherein each reset signal of the plurality of reset signals is generated by shifting a previous reset signal,
- wherein the source clock signal has twice the frequency of the phase clock signals,
- wherein the plurality of the phase clock signals include first to fourth phase clock signals having the constant phase difference,
- wherein the plurality of the reset signals include first positive and negative reset signals corresponding to the first phase clock signal, second positive and negative reset signals corresponding to the second phase clock signal, third positive and negative reset signals corresponding to the third phase clock signal and fourth positive and negative reset signals corresponding to the fourth phase clock signal.
4 more elements
A method for operating a semiconductor device, comprising the steps of:
- generating a plurality of reset signals in response to a control signal by shifting a previous reset signal of the plurality of reset signals, wherein the plurality of the reset signals have different activation timings with adjacent ones having the same phase difference;
- and
- operating in response to the plurality of the reset signals and dividing a frequency of a source clock signal to generate a plurality of phase clock signals with adjacent ones having the same phase difference,
- wherein the source clock signal has twice the frequency of the phase clock signals,
- wherein the plurality of the phase clock signals include first and second phase clock signals having the constant phase difference,
- wherein the plurality of the reset signals include first positive and negative reset signals corresponding to the first phase clock signal and second positive and negative reset signals corresponding to the second phase clock signal.
3 more elements
A semiconductor device having a multi-phase clock signal generating means, the multi-phase clock signal generating means comprising:
- a plurality of shifters for shifting an input signal in response to first and second clock signals and subsequently producing a plurality shifting signals through latch units, wherein the first clock signal is out of phase with the second clock signal and the subsequently produced shifting signals are out of phase with adjacent ones having a constant phase difference;
- and
- a plurality of clock signal generating units for generating clock signals using the first and second clock signals and the plurality shifting signals, wherein each of the clock signal generating units has a signal path having a latch unit, wherein the signal path is controlled by the first or second clock signal and wherein an input signal of the clock signal generating unit is provided by a feedback loop.
Dependencies are inferred from the claim text.