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US 8,283,961 B2Granted
Delay line circuit
AssigneeMicron Technology, Inc.
InventorJongtae Kwak
Life of this patent
Estimating the term…
Abstract
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.
Claims28
A delay locked loop circuit, comprising:
- serially-coupled delay line circuits, each delay line circuit having a first input node, a second input node and an output node, each delay line circuit configured to propagate a signal received on one of the first input node and the second input node to the output node in a time T;
- a shift register circuit coupled to the delay line circuits that is configured to select at least one of the serially coupled delay line circuits by enabling a selected one of the first and second input nodes of the delay line circuits;
- and
- a phase mixer circuit to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay line circuit of the serially coupled delay line circuits, the phase mixer circuit configured to provide a controllable internal propagation time.
1 more element
A synchronous circuit, comprising:
- a plurality of delay line circuits coupled in series, each delay line circuit having a first input node, a second input node and an output node, each delay line circuit configured to propagate a signal received on one of the first input node and second input node to the output node in a time T;
- a shift register circuit coupled to the delay line circuits to select at least one of the plurality of delay line circuits by enabling a selected one of the first and second input nodes of the delay line circuits;
- and
- a mixer circuit to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay line circuit of the plurality of delay line circuits, the mixer circuit configured to provide a controllable internal propagation time.
1 more element
A delay locked loop, comprising:
- serially-coupled delay line elements, each delay line element having a first and second input nodes and an output node, each delay line element configured to propagate a signal received on one of the first and second input nodes to the output node in a time T;
- a shift register coupled to the delay line elements to select one of the delay line elements by enabling one of the first and second input nodes;
- and
- a phase mixer to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay line element of the serially coupled delay line elements, the phase mixer configured to generate a first one (Y) of the first and second mixed output signals according to a relation Y=A*(1−K)+B*K, where A is a signal received at a first node of the phase mixer, and B is a signal received at a second node of the phase mixer, and wherein K is a weight factor that varies between zero and one.
1 more element
A delay locked loop, comprising:
- a delay line having serially coupled delay elements, each of the delay elements including a first input node, a second input node and an output node, each of the delay elements configured to propagate a signal received on one of the first input node and second input node to the output node in a time T;
- a shift register coupled to the elements to select at least one of the elements by enabling a selected one of the first and second input nodes of the elements;
- and
- a phase mixer to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay element of the delay elements associated with the delay line, the phase mixer including first parallel coupled inverters positioned between a first input node and an output node of the phase mixer, and second parallel coupled inverters positioned between a second input node and the output node of the phase mixer, wherein the first and second parallel coupled inverters are controllable to alter a propagation time of the first and second parallel coupled inverters.
1 more element
A synchronous circuit, comprising:
- a plurality of delay line elements coupled in series, each delay line element having a first input node, a second input node and an output node, each delay line element configured to propagate a signal received on one of the first input node and second input node to the output node in a time T;
- a shift register coupled to the delay line elements to select at least one of the plurality of delay line elements by enabling a selected one of the first and second input nodes of the delay line elements;
- and
- a mixer to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay line element of the plurality of delay line elements, the mixer circuit configured to generate a first one (Y) of the first and second mixed output signals according to a relation Y=A*(1−K)+B*K, where A is a signal received at a first node of the mixer, B is a signal received at a second node of the mixer, and K is a weighting parameter that varies between zero and one.
1 more element
A synchronous circuit, comprising:
- a plurality of delay line circuits coupled in series, each delay line circuit having a first input node, a second input node and an output node, each delay line circuit configured to propagate a signal received on one of the first input node and second input node to the output node in a time T;
- a shift register circuit coupled to the delay line circuits to select at least one of the plurality of delay line circuits by enabling a selected one of the first and second input nodes of the delay line circuits;
- and
- a mixer circuit to provide at least one of a first mixed output signal or a second mixed output signal to the second input node of each delay line circuit of the plurality of delay line circuits, the mixer circuit including a first plurality of parallel coupled inverters positioned between a first input node and an output node of the mixer circuit, and a second plurality of parallel coupled inverters positioned between a second input node and the output node of the mixer circuit, wherein the first and second parallel coupled inverters are coupled to a weight factor module to alter a propagation time of the first and second parallel coupled inverters.
1 more element
Dependencies are inferred from the claim text.