Minimal bubble voltage regulator

A digital voltage regulator component of an integrated circuit, the integrated circuit having a power supply and logic circuits, the digital voltage regulator comprising:

• a delay chain having a data delay rail and a data complement delay rail, the data and data complement delay rails being interconnected through pairs of cross-coupled inverters, wherein the delay chain includes a plurality of stages;
• a sampling circuit having a plurality of differential input flip-flops each connected to a corresponding stage of the delay chain to capture a corresponding delay chain value, wherein each differential input is connected to a data output and data complement output associated with the corresponding stage of the delay chain to capture the corresponding delay chain value, and wherein each differential input flip-flop includes first and second pre-charge nodes, the first pre-charge node connected to a first transistor, the second pre-charge node connected to a second transistor, wherein a data input line is connected directly to the first transistor and a data complement line is connected directly to the second transistor;
• and
• a decoder circuit having a plurality of inputs, each input connected to an output of a corresponding differential input flip-flop in the sampling circuit to receive the corresponding delay chain value, wherein the decoder circuit is operable to calculate a power supply voltage based on the plurality of inputs, the decoder circuit including an output that when asserted indicates that a power supply voltage has fallen below a predetermined threshold value.