Frequency-doubling delay locked loop
AssigneeMosaid Technologies Incorporated
InventorPaul W. Demone
Life of this patent
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Abstract
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
Claims5
A delay locked loop (DLL) for providing an output clock signal in response to an input clock signal, the DLL comprising:
- a delay line for receiving the input clock signal, the delay line having a plurality of serially coupled delay stages for providing respective delay stage outputs;
- a plurality of combining circuit cells, each of the combining cells having inputs respectively coupled to ones of a plurality of the delay stage outputs, each of the combining cells providing a cell output signal, a plurality of the delay stage outputs each triggering a first edge of a respective cell output signal;
- and
- a selector responsive to a first selection control signal for selecting one of the cell output signals to provide an output clock signal.
A method of providing an output clock signal in response to an input clock signal comprising:
- receiving an input clock signal;
- providing a plurality of delayed versions of the input clock signal at respective delay stages;
- generating a plurality of output signals, outputs of a plurality of the delay stages each triggering a first edge of a respective output signal;
- and
- selecting one of the plurality of output signals to provide an output clock signal.
Dependencies are inferred from the claim text.