US 8,283,941 B2 · Alternating current (AC) stress test circuit, method for evaluating AC stress induced hot carrier injection (HCI) degradation, and test structure for HCI degradation evaluation

Abstract

An AC stress test circuit for HCI degradation evaluation in semiconductor devices includes a ring oscillator circuit, first and second pads, and first and second isolating switches. The ring oscillator circuit has a plurality of stages connected in series to form a loop. Each of the stages comprises a first node and a second node. The first and second isolating switches respectively connect the first and second pads to the first and second nodes of a designated stage and both are switched-off during ring oscillator stressing of the designated stage. The present invention also provides a method of evaluating AC stress induced HCI degradation, and a test structure.

Claims18

Dependent claims

An alternating current (AC) stress test circuit for hot carrier injection (HCI) degradation evaluation in semiconductor devices, comprising:

a ring oscillator circuit having a plurality of stages electrically connected in series between an input terminal and an output terminal electrically connected with the input terminal and whereby forming a loop, wherein each of the stages comprises a first node and a second node, a designated one of the stages serves as device under test (DUT);
a first isolating switch and a second isolating switch, respectively electrically connecting the first node and the second node of the DUT;
an input means being electrically connected to the first isolating switch and for applying a gate on voltage to the first node through the first isolating switch to bias the DUT;
and
an output means being electrically connected to the second isolating switch and for measuring a current flowing from the second node through the second isolating switch.

2 more elements

A method for evaluating AC stress induced HCI degradation in semiconductor devices, wherein the method is adapted to be performed on an AC stress test circuit, the AC stress test circuit comprises a ring oscillator circuit, a first pad, a second pad, a first isolating switch and a second isolating switch, the ring oscillator circuit having a plurality of stages electrically connected in series between an input terminal and an output terminal electrically connected with the input terminal and whereby forming a loop, each of the stages comprising a first node and a second node, a designated one of the stages serving as device under test (DUT), the first isolating switch and the second isolating switch respectively electrically connecting the first pad and the second pad to the first node and the second node of the DUT, the method comprises steps of:

during a stress mode of the AC stress test circuit, enabling the AC stress test circuit to apply an internal AC stress to the DUT while the first and second isolating switches both being switched-off;
and
during a measurement mode of the AC stress test circuit, disabling the AC stress test circuit, switching on both the first and second isolating switches, applying a gate-on voltage to the first node through the first pad and measuring a current flowing from the second node through the second pad.

A test structure for HCI degradation evaluation in semiconductor devices, the test structure comprising:

an AC stress test circuit comprising:
a ring oscillator circuit having a plurality of stages connected in series between an input terminal and an output terminal electrically connected with the input terminal and whereby forming a loop, wherein each of the stages comprises a first node and a second node, a designated one of the stages serves as a first DUT;
a first probing pad and a second probing pad;
and a first isolating switch and a second isolating switch, respectively electrically connecting the first probing pad and the second probing pad to the first node and the second node of the first DUT, wherein the first probing pad applies a gate on voltage to the first node through the first isolating switch to bias the first DUT and the second probing pad measures a current flowing from the second node through the second isolating switch;
and a direct current (DC) stress test circuit independent from the AC stress test circuit, the DC stress test circuit comprising:
a second DUT having a same circuit configuration as the first DUT and comprising a third node and a fourth node;
and a third pad and a fourth pad, respectively electrically connected to the third node and the fourth node.

4 more elements

Dependencies are inferred from the claim text.

Alternating current (AC) stress test circuit, method for evaluating AC stress induced hot carrier injection (HCI) degradation, and test structure for HCI degradation evaluation

Life of this patent

Alternating current (AC) stress test circuit, method for evaluating AC stress induced hot carrier injection (HCI) degradation, and test structure for HCI degradation evaluation

Life of this patent

Abstract

Claims18