Systems and methods for built in self test jitter measurement

A method for built in self-test (BiST) jitter measurement using an integrated circuit configured for built in self-test (BiST) jitter measurement, comprising:

• generating a constant current;
• providing a jitter voltage signal from a time-to-voltage converter in the integrated circuit, wherein the jitter voltage signal is a voltage representation of jitter in a clock/data signal input for the built in self-test jitter measurement;
• providing feedback to the time-to-voltage converter, wherein feedback circuitry provides a ramp slope for the time-to-voltage converter, and wherein the feedback circuitry adjusts a gate bias for a transistor in the time to voltage converter to provide a linearly increasing voltage ramp;
• providing the jitter voltage signal to automatic testing equipment (ATE);
• and
• performing jitter measurements using the ATE.

A wireless device configured for built in self-test (BiST) jitter measurement, comprising:

• a processor;
• memory in electronic communication with the processor;
• a transceiver;
• and
• an integrated circuit configured for built-in self-test jitter measurement, including:
• a time-to-voltage converter, wherein the time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input for the built in self-test jitter measurement;
• feedback circuitry for the time-to-voltage converter, wherein the feedback circuitry provides a ramp slope for the time-to-voltage converter, and wherein the feedback circuitry adjusts a gate bias for a transistor in the time to voltage converter to provide a linearly increasing voltage ramp;
• a calibration controller, wherein the calibration controller provides control signals to the time-to-voltage converter for process-independent calibration;
• and
• a sample-and-hold (S/H) circuit, wherein the S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

An apparatus for built in self-test (BiST) jitter measurement, comprising:

• means for generating a constant current;
• means for providing a jitter voltage signal by a time-to-voltage converter, wherein the jitter voltage signal is a voltage representation of jitter in a clock/data signal input for the built in self-test litter measurement;
• means for providing feedback to the time-to-voltage converter, wherein the means for providing feedback provides a ramp slope for the time-to-voltage converter, and wherein the means for providing feedback adjusts a gate bias for a transistor in the time to voltage converter to provide a linearly increasing voltage ramp;
• means for providing the jitter voltage signal to automatic testing equipment (ATE);
• and
• means for performing jitter measurements using the ATE.

A computer-program product for a wireless device configured for built in self-test (BiST) jitter measurement, the computer-program product comprising a non-transitory computer-readable medium having instructions thereon, the instructions comprising:

• code for generating a constant current;
• code for providing a jitter voltage signal by a time-to-voltage converter, wherein the jitter voltage signal is a voltage representation of jitter in a clock/data signal input for the built in self-test jitter measurement;
• code for providing feedback to the time-to-voltage converter, wherein the feedback provides a ramp slope for the time-to-voltage converter, and wherein the feedback adjusts a gate bias for a transistor in the time to voltage converter to provide a linearly increasing voltage ramp;
• code for providing the jitter voltage signal to automatic testing equipment (ATE);
• and
• code for performing built in self-test jitter measurements using the ATE.