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US 8,283,781 B2Granted
Semiconductor device having pad structure with stress buffer layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng, Tzuan-Horng Liu, Tzu-Wei Chiu, Chao-Wen Shih
Life of this patent
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Abstract
A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.
Claims20
A semiconductor device, comprising:
- a metal pad overlying a semiconductor substrate;
- a passivation layer overlying the metal pad, the passivation layer covering an edge portion of the metal pad and exposing a first portion of the metal pad;
- a ring-shaped layer overlying the passivation layer and the metal pad, the ring-shaped layer covering an edge portion of the passivation layer and exposing a second portion of the metal pad, wherein the second portion of the metal pad is within the first portion of the metal pad;
- an under-bump metallization (UBM) layer overlying the ring-shaped layer and electrically connected to the second portion of the metal pad;
- and
- a metal bump overlying the UBM layer.
3 more elements
A semiconductor device, comprising:
- a metal pad overlying a semiconductor substrate;
- a passivation layer overlying the metal pad and exposing a portion of the metal pad;
- an interconnect line overlying the passivation layer and electrically connected to the exposed portion of the metal pad;
- a barrier layer overlying the interconnect line and exposing a portion of the interconnect line;
- a ring-shaped layer overlying the barrier layer and electrically connected to the exposed portion of the interconnect line,
- an under-bump metallization (UBM) layer overlying the ring-shaped layer and electrically connected to the exposed portion of the interconnect line;
- and
- a bump overlying the UBM layer.
5 more elements
A process, comprising:
- providing a semiconductor substrate having a conductive region;
- forming a dielectric layer overlying the semiconductor substrate;
- forming a first opening in the dielectric layer to expose a portion of the conductive region;
- forming a ring-shaped layer overlying the dielectric layer, exposing at least a portion of the exposed portion of the conductive region;
- forming an under-bump metallization (UBM) layer overlying the ring-shaped layer, the dielectric layer and the conductive region;
- forming a mask layer with a second opening overlying the UBM layer;
- forming a conductive material layer in the second opening of the mask layer, the conductive material layer electrically connected to the UBM layer;
- and
- removing the mask layer.
6 more elements
Dependencies are inferred from the claim text.