Back to results
US 8,283,771 B2Granted
Multi-die integrated circuit device and method
AssigneeIntel Corporation
InventorsDinesh Somasekhar, Tanay Karnik, Jianping Xu, Yibin Ye
Life of this patent
Estimating the term…
Abstract
In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.
Claims17
An apparatus comprising:
- a first die coupled to a second die;
- and
- vias disposed through the second die to provide power references to the first die, the vias being positioned along a first axis without overlapping circuit sections in the second die,
- wherein the vias are disposed along lines in a direction of the first axis, the lines being parallel to and between two or more tracks having the circuit sections in the second die, and wherein the vias being on either side of the two or more tracks,
- wherein the second die has at least first, second, and third metal line layers, the first metal line layer being closer to circuitry in the second die, followed by the second and third metal line layers, and
- wherein the first metal line layer is used to provide contact pads for the vias, the second layer is used to couple like vias together, and the third layer is used to interconnect portions of circuit sections within the second die with one another.
3 more elements
A chip comprising:
- a substrate with circuit components;
- a metal layer having a plurality of through-silicon-via (TSV) landing pads for passing through the substrate, the TSV landing pads disposed along lines that are parallel to two or more tracks having the circuit components, wherein the TSV landing pads are positioned between and on either side of the two or more tracks without overlapping the two or more tracks;
- and
- at least first, second, and third metal line layers, the first metal line layer being closer to the circuit components in the chip, followed by the second and third metal line layers, and
- wherein the first metal line layer is used to provide contact pads for the TSVs, the second layer is used to couple like TSVs together, and the third layer is used to interconnect portions of circuit components with one another.
2 more elements
An integrated circuit (IC) package comprising:
- a processor die coupled to a memory die in a stack configuration, the memory die having memory banks each including spaced apart memory bank sections, the memory bank sections arranged inside two or more tracks;
- and
- through-silicon-vias (TSVs) disposed through the memory die to provide power references to the processor and memory dies from outside of the IC package, the TSVs being positioned between and on either side of the two or more tracks without overlapping the two or more tracks,
- wherein the memory die has at least first, second, and third metal line layers, the first metal line layer being closer to circuitry in the memory die, followed by the second and third metal line layers, and
- wherein the first metal line layer is used to provide landing pads for the TSVs, the second metal line layer is used to couple like TSVs together, and the third metal line layer is used to interconnect portions of the memory bank sections within the memory die with one another.
2 more elements
Dependencies are inferred from the claim text.