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US 8,283,756 B2Granted
Electronic component with buffer layer
AssigneeInfineon Technologies AG
InventorsIvan Galesic, Joachim Mahler, Alexander Heinrich, Khalil Hosseini
Life of this patent
Estimating the term…
Abstract
An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip.
Claims18
An electronic component comprising:
- a metal substrate;
- a semiconductor chip configured to be attached to the metal substrate;
- a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate and reduce stress on the semiconductor chip caused by thermal contraction of the metal substrate, wherein the buffer layer extends across less than an entire bottom surface of the semiconductor chip, wherein the buffer layer comprises a plurality of separate and distinct buffer layer elements, wherein at least one of the buffer layer elements is positioned adjacent to a corner of the semiconductor chip and extends laterally substantially beyond the bottom surface of the semiconductor chip, and wherein the buffer layer comprises Ag, In, Pt, Fe, Au, Pd, or Ni;
- and
- intermetallic phases attaching the semiconductor chip to the buffer layer and to the metal substrate.
2 more elements
An electronic component comprising:
- a metal substrate;
- a semiconductor chip configured to be attached to the metal substrate;
- a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate and reduce stress on the semiconductor chip caused by thermal contraction of the metal substrate, wherein the buffer layer extends across less than an entire bottom surface of the semiconductor chip, wherein the buffer layer comprises a plurality of separate and distinct buffer layer elements, wherein at least one of the buffer layer elements is positioned adjacent to a corner of the semiconductor chip and extends substantially beyond the bottom surface of the semiconductor chip, wherein the buffer layer comprises a multi-layer stack, and wherein the multi-layer stack includes a Ni layer, a Pd layer, and an Au layer;
- and
- intermetallic phases attaching the semiconductor chip to the buffer layer and to the metal substrate.
2 more elements
An electronic component comprising:
- a metal substrate;
- a semiconductor chip configured to be attached to the metal substrate;
- a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate and reduce stress on the semiconductor chip caused by thermal contraction of the metal substrate, wherein the buffer layer extends across less than an entire bottom surface of the semiconductor chip, wherein the buffer layer comprises a plurality of separate and distinct buffer layer elements, wherein at least one of the buffer layer elements is positioned adjacent to a corner of the semiconductor chip and extends laterally substantially beyond the bottom surface of the semiconductor chip, and wherein the buffer layer is about 0.5 to 5 μm thick;
- and
- intermetallic phases attaching the semiconductor chip to the buffer layer and to the metal substrate.
2 more elements
A semiconductor device comprising:
- a metal substrate;
- a semiconductor chip configured to be attached to the metal substrate;
- and
- buffering means positioned between the metal substrate and the semiconductor chip for mechanically decoupling the semiconductor chip and the metal substrate and reducing stress on the semiconductor chip caused by thermal contraction of the metal substrate, wherein the buffering means extends across less than an entire bottom surface of the semiconductor chip, wherein the buffering means comprises a plurality of separate and distinct buffer layer elements, and wherein at least one of the buffer layer elements is positioned adjacent to a corner of the semiconductor chip and extends substantially beyond the bottom surface of the semiconductor chip;
- and
- intermetallic phases attaching the semiconductor chip to the buffering means and to the metal substrate.
3 more elements
Dependencies are inferred from the claim text.