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US 8,283,727 B1Granted
Circuit with electrostatic discharge protection
AssigneeCypress Semiconductor Corporation
InventorsAndrew Walker, Helmut Puchner, Sai Dhanraj, Kevin Jang
Life of this patent
Estimating the term…
Abstract
A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.
Claims19
A circuit, comprising:
- a trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge (ESD) event, the trigger device comprising an isolation structure interposed between a gate oxide and an extended drain region, wherein a portion of the extended drain region proximate the isolation structure is substantially metal-free.
A circuit, comprising:
- a silicon controlled rectifier (SCR) and a trigger device formed upon a substrate and configured to collectively protect a circuit component from damage during an electrostatic discharge (ESD) event, wherein at least a portion of the SCR is formed upon a deep N-well formed in the substrate and wherein the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region, wherein a portion of the extended drain region proximate the isolation structure is substantially metal-free.
A circuit, comprising:
- a silicon controlled rectifier (SCR) having a first terminal disposed in an N-well and second terminal disposed in a P-well, the first terminal connected to a node to be protected and the second terminal connected to ground;
- a trigger device disposed between the first and second terminals and configured to be activated at a trigger voltage, the trigger device including a gate and a gate oxide, an extended drain region and a first isolation structure positioned between the gate and the extended drain region and a second isolation structure positioned between the extended drain region and the first terminal, wherein a first portion of the gate overlays the gate oxide and a second portion of the gate overlays and contacts the first isolation structure to at least partially define the trigger voltage.
Dependencies are inferred from the claim text.