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US 8,283,725 B2Granted
Semiconductor device
AssigneeSeiko Instruments Inc.
InventorHiroaki Takasu
Life of this patent
Estimating the term…
Abstract
In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection.
Claims8
A semiconductor device, comprising:
- an n-type metal oxide semiconductor transistor for electrostatic discharge protection disposed on a semiconductor substrate, placed between an external connection terminal and an internal circuit region so that an internal element disposed in the internal circuit region is protected from electrostatic discharge breakdown;
- a p-type region disposed on the semiconductor substrate in contact with a side of a drain region of the n-type metal oxide semiconductor transistor that is opposite to a gate electrode of the n-type metal oxide semiconductor transistor, the drain region is between the gate electrode and the p-type region;
- an n-type region placed apart from the drain region opposite to the gate electrode of the n-type metal oxide semiconductor transistor, fully isolated from the drain region by the p-type region, having no connection to the drain region through another n-type region, and configured to receive a signal from the external connection terminal;
- and
- a shallow trench region surrounding the n-type metal oxide semiconductor transistor, the p-type region, and the n-type region for isolation.
2 more elements
A semiconductor device, comprising:
- a first and a second n-type metal oxide semiconductor transistor for electrostatic discharge protection disposed on a semiconductor substrate;
- a first p-type region disposed on the semiconductor substrate in contact with a side of a drain region of the first n-type metal oxide semiconductor transistor that is opposite to a gate electrode of the first n-type metal oxide semiconductor transistor;
- a second p-type region disposed on the semiconductor substrate in contact with a side of a drain region of the second n-type metal oxide semiconductor transistor that is opposite to a gate electrode of the second n-type metal oxide semiconductor transistor;
- and
- an n-type region between the first and second p-type regions, fully isolated from the drain regions of each of the first and second n-type regions of each of the first and second n-type metal oxide semiconductor transistors, and having no connection to the drain regions through another n-type region, and configured to receive a signal from the external connection terminal.
2 more elements
Dependencies are inferred from the claim text.