Semiconductor device having an enhanced well region
AssigneeBroadcom Corporation
InventorAkira Ito
Life of this patent
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AssigneeBroadcom Corporation
InventorAkira Ito
Estimating the term…
An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.
A metal oxide silicon (MOS) field effect transistor device, comprising:
A metal oxide silicon (MOS) field effect transistor device, comprising:
A metal oxide silicon (MOS) field effect transistor device, comprising:
Dependencies are inferred from the claim text.