Method and apparatus for buried word line formation
AssigneeRexchip Electronics Corporation
InventorsYung-Chang Lin, Sheng-Chang Liang
Life of this patent
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Abstract
An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.
Claims29
An integrated circuit, comprising:
- a vertical transistor formed in a substrate, the vertical transistor comprising a channel region arranged between a lower junction region and a upper junction region;
- a word line arranged adjacent the channel region in a word line trench;
- a bit line disposed below the word line in a bit line trench arranged below the vertical transistor;
- and
- a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line;
- wherein an etching rate of the separating layer approaches that of the substrate.
An integrated circuit with a memory cell, comprising:
- a word line disposed in a word line trench of a substrate;
- a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line;
- and
- a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line;
- wherein an etching rate of the separating layer approaches that of the substrate.
A memory device comprising a plurality of interconnected memory cells, each of the memory cells comprising:
- a word line disposed in a word line trench of a substrate;
- a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line;
- and
- a separating layer disposed above the bit line in the bit line trench that separates the word line from the buried bit line;
- wherein an etching rate of the separating layer approaches that of the substrate.
A method of manufacturing an integrated circuit with a memory cell, comprising:
- forming a bit line in a bit line trench of a substrate;
- forming a separating layer above the bit line in the bit line trench;
- forming a word line trench above and extending orthogonal to the bit line in the substrate;
- and
- forming a word line in the word line trench;
- wherein the separating layer separates the word line from the bit line and an etching rate of the separating layer approaches that of the substrate.
Dependencies are inferred from the claim text.