Semiconductor memory device having vertical channel transistor and method for fabricating the same

A semiconductor memory device, comprising:

• a first active region and a second active region, wherein each of the first active region and the second active region has a first side surface and a second side surface, and the first side surface of the first active region faces at least a portion of the second side surface of the second active region;
• source regions formed above the first and second active region;
• drain regions formed under the first and second active region;
• a gate electrode disposed between the first side surface of the first active region and the second side surface of the second active region;
• a word line connected to the gate electrode;
• a bit line contact plug formed to contact the drain region;
• a bit line connected to the bit line contact plug, going across any one of the first and second active regions;
• and
• a storage node contact plug contacting the source region,
• wherein the first active region and the second active region are spaced apart in a widthwise direction and the first active region and the second active region, which shares the gate electrode with the first active region, are staggered in a lengthwise direction,
• wherein the first active region and the second active region are staggered in the lengthwise direction in that the first active region extends from a first lengthwise position in the lengthwise direction to a second lengthwise position and the second active region extends from the second lengthwise position in the lengthwise direction to a third lengthwise position, wherein the second lengthwise position lies between the first lengthwise position and the third lengthwise position in the lengthwise direction.

A semiconductor memory device, comprising:

• a first active region and a second active region, wherein each of the first active region and the second active region has a first side surface and a second side surface, and the first side surface of the first active region faces at least a portion of the second side surface of the second active region;
• source regions formed above the first and second active region;
• drain regions formed under the first and second active region;
• a common gate electrode disposed between the first side surface of the first active region and the second side surface of the second active region;
• a word line connected to the common gate electrode;
• a bit line contact plug formed to contact the drain region;
• a bit line connected to the bit line contact plug, going across any one of the first and second active regions;
• a storage node contact plug contacting the source region;
• and
• a contact spacer surrounding a side surface of the bit line contact plug and formed of an insulating material,
• wherein each of the first active region and the second active region have a first partial active region and a second partial active region;
• and
• wherein the first partial active region of the first active region and the second partial active region of the second active region are arranged in a direction perpendicular to the lengthwise direction of the first and the second active region, and
• wherein the contact spacer completely separates the first partial active region of the first active region and the second partial active region of the second active region from each other.