Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width
AssigneeMicron Technology, Inc.
InventorsLequn Liu, Yongjun Jeff Hu, Anish A. Khandekar
Life of this patent
Estimating the term…
Abstract
Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.
Claims17
A method of forming a semiconductor device, comprising:
- forming an oxide over a semiconductor and a gate, the gate adjacent to the semiconductor;
- implanting ions into at least a portion of the semiconductor to form a plurality of diffusion regions therein after forming the oxide over the semiconductor and the gate;
- forming a dielectric over the oxide;
- annealing the dielectric formed over the oxide;
- and
- forming openings through the dielectric to provide access to the plurality of diffusion regions in the semiconductor.
A semiconductor device, comprising:
- at least two diffusion regions in a semiconductor, wherein each diffusion region is adjacent to one of at least two gates formed adjacent to a surface of semiconductor;
- a plurality of isolation regions, each isolation region of the plurality of isolation regions configured to electrically isolate adjacent diffusion regions of the at least two diffusion regions;
- an oxide over the at least two gates and the surface of the semiconductor;
- and
- a dielectric over the oxide, the dielectric having a plurality of openings extending therethrough for providing access to at least some of the at least two diffusion regions in the semiconductor;
- wherein the at least two diffusion regions each comprise a first width extending across each diffusion region and to adjacent isolation regions at a first depth below the surface of the semiconductor and a second width extending across each diffusion region and to adjacent isolation regions at a second depth below the surface of the semiconductor, wherein the second depth is closer to the surface of the semiconductor than the first depth;
- and
- wherein the second width of at least some of the at least two diffusion regions is less than about 40% greater than the first width.
A semiconductor device, comprising:
- a plurality of diffusion regions in a semiconductor, wherein each diffusion region is adjacent to one of a plurality of gates formed adjacent to a surface of the semiconductor;
- a plurality of isolation regions, each isolation region of the plurality of isolation regions configured to electrically isolate adjacent diffusion regions of the plurality of diffusion regions;
- an oxide over the surface of the semiconductor and the plurality of gates adjacent to the surface of the semiconductor;
- and
- a dielectric over the oxide, the dielectric having a plurality of openings extending therethrough for providing access to at least some of the plurality of diffusion regions in the semiconductor;
- wherein the plurality of diffusion regions each comprise a first width extending across the diffusion region and to adjacent isolation regions of about 30 nanometers or less at a first depth below the surface of the semiconductor and a second width extending across the diffusion region and to adjacent isolation regions at a second depth below the surface of the substrate, wherein the second depth is closer to the surface of the semiconductor than the first depth, and wherein the second width of at least one of the diffusion regions is less than about 40% greater than the first width.
Dependencies are inferred from the claim text.