Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same

An organic light emitting diode (OLED) display device comprising:

• a substrate;
• a gate electrode disposed on the substrate;
• a gate insulating layer disposed on the gate electrode;
• a polycrystalline silicon layer comprising a semiconductor layer pattern disposed on the gate insulating layer and including a channel region, a source region and a drain region;
• an etch stop layer pattern disposed on the channel region of the semiconductor layer pattern and having a thickness of 20 to 60 nm, wherein a size of a grain forming the channel region of the semiconductor layer pattern is 1 to 10 μm, and a size of a grain forming the source and drain regions is 0.5 to 2 μm;
• an amorphous silicon layer doped with n or p-type impurities disposed on the source and drain regions of the polycrystalline silicon layer;
• source and drain electrodes disposed on the amorphous silicon layer and electrically contacting the source and drain regions of the semiconductor layer pattern;
• a first electrode electrically connected to one of the source and drain electrodes;
• an organic layer disposed on the first electrode and including an emission layer;
• and
• a second electrode disposed on the organic layer.

A method of fabricating a thin film transistor, comprising:

• preparing a substrate;
• forming a gate electrode on the substrate;
• forming a gate insulating layer on the gate electrode;
• forming an amorphous silicon layer on the gate insulating layer;
• forming an etch stop layer pattern to a thickness of 20 to 60 nm on a predetermined region of the amorphous silicon layer;
• irradiating a laser on the entire surface of the substrate to crystallize the amorphous silicon layer to form a polycrystalline silicon layer including a channel region, a source region and a drain region, a size of a grain forming the channel region of the semiconductor layer pattern being 1 to 10 μm, and a size of a grain forming the source and drain regions being 0.5 to 2 μm;
• forming an amorphous silicon layer doped with n or p-type impurities on the entire surface of the substrate where the etch stop layer pattern is formed after forming the polycrystalline silicon layer, and patterning the polycrystalline silicon layer and the amorphous silicon layer doped with n or p-type impurities;
• forming a metal layer for source and drain electrodes on the entire surface of the substrate where the etch stop layer pattern is formed;
• and
• patterning the metal layer to form source and drain electrodes electrically connected to the source and drain regions.