Method for forming one transistor DRAM cell structure
AssigneeFreescale Semiconductor, Inc.
InventorsJames D. Burnett, Brian A. Winstead
Life of this patent
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Abstract
A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.
Claims18
A method for forming a one-transistor dynamic random access memory (DRAM) cell, comprising:
- forming a gate over a body region of the DRAM memory cell, the body of the DRAM memory cell formed in a semiconductor layer having a first conductivity type;
- forming first and second source/drain regions in the semiconductor layer adjacent to, and on opposite sides of, the body region, wherein the first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region, wherein
- the first source/drain region comprises a first silicide layer extending under the gate,
- the second source/drain region comprises a second silicide layer extending under the gate and a source/drain extension region extending under the gate, and
- the first source/drain region is devoid of a source/drain extension region.
A method for forming a one-transistor dynamic random access memory (DRAM) cell, comprising:
- forming a transistor having a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region, wherein the first source/drain region comprises a Schottky diode junction with the body region and the second source/drain region comprises an n-p diode junction with the body region,
- wherein the first source/drain region comprises a first silicide layer extending under the gate,
- the second source/drain region comprises a second silicide layer extending under the gate and a source/drain extension region extending under the gate,
- wherein each of the first and second source/drain regions comprise a deep source/drain region and wherein the first source/drain region is devoid of a source/drain extension region.
A method for forming a one-transistor dynamic random access memory (DRAM) cell, comprising:
- forming a transistor having a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region, wherein the first source/drain region comprises a Schottky diode junction with the body region and the second source/drain region comprises an n-p diode junction with the body region and an ohmic contact in series with the n-p diode junction,
- wherein the first source/drain region comprises a first silicide layer extending under the gate,
- the second source/drain region comprises a second silicide layer extending under the gate and a source/drain extension region extending under the gate,
- wherein each of the first and second source/drain regions comprise a deep source/drain region and wherein the first source/drain region is devoid of a source/drain extension region, and
- wherein:
- when the transistor is characterized as an N-channel transistor, the majority carriers are removed from the body region via the Schottky diode junction during a write operation of the DRAM cell in response to a potential at the first source/drain region being lower than a potential at the second source/drain region, and
- when the transistor is characterized as a P-channel transistor, the majority carriers are removed from the body region via the Schottky diode junction during a write operation of the DRAM cell in response to a potential at the first source/drain region being higher than a potential at the second source/drain region.
Dependencies are inferred from the claim text.