US 8,283,237 B2Granted

Fabrication of through-silicon vias on silicon wafers

AssigneeApplied Materials, Inc.

InventorsNagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami

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Abstract

A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.

Claims34

Dependent claims

A through-silicon via fabrication method comprising:

(a) forming a silicon plate having a front surface, one or more features therein, and a back surface;
(b) providing a carrier for supporting the silicon plate;
(c) forming a substrate by bonding the front surface of the silicon plate to the carrier using an adhesive layer therebetween to expose the back surface of the silicon plate;
(d) depositing a silicon nitride passivation layer on the exposed back surface of the silicon plate of the substrate;
(e) etching a plurality of through holes in the silicon plate, the through holes comprising sidewalls and a bottom wall;
(f) depositing in each of the through holes:
(i) an oxide liner on the sidewalls and bottom wall of the through holes;
(ii) a sealing layer over the oxide liner, the sealing layer comprising silicon nitride;
and
(iii) a metallic conductor over the sealing layer to form a plurality of through-silicon vias;
(g) after (f), chemical mechanical polishing the back surface of the silicon plate to expose the to portions of the metallic conductor deposited into the through holes of the silicon plate;
(h) removing a native oxide film formed on the exposed portions of the metallic conductor in the through holes by (1) maintaining the substrate at a first temperature of from about 100° C. to about 220° C. in a process zone comprising a pair of process electrodes, (2) introducing into the process zone, a reducing gas comprising ammonia or hydrogen, and (3) applying a first power to the process electrodes;
and
(i) after (h), performing a silane soaking step comprising (1) maintaining the substrate at a second temperature of from about 100° C. to about 220° C. in the process zone comprising the pair of process electrodes, (2) introducing into the process zone, a soaking gas comprising silane, and (3) applying a second power to the process electrodes.

11 more elements

A through-silicon via fabrication method comprising:

(a) forming a silicon plate having a front surface, one or more features therein, and a back surface;
(b) providing a carrier for supporting the silicon plate;
(c) forming a substrate by bonding the front surface of the silicon plate to the carrier using an adhesive layer therebetween to expose the back surface of the silicon plate;
(d) depositing a silicon nitride passivation layer on the exposed back surface of the silicon plate of the substrate;
(e) etching a plurality of through holes in the silicon plate, the through holes comprising sidewalls and a bottom wall;
(f) depositing in each of the through holes:
(1) an oxide liner on the sidewalls and bottom wall of the through holes;
(2) a sealing layer over the oxide liner, the sealing layer comprising silicon nitride;
and
(3) a metallic conductor over the sealing layer to form a plurality of through-silicon vias;
(g) removing a native oxide film formed on the exposed portions of the metallic conductor in the through holes by (1) maintaining the substrate at a first temperature of from about 100° C. to about 220° C. in a process zone comprising a pair of process electrodes, (2) introducing into the process zone, a reducing gas comprising ammonia or hydrogen, and (3) applying a first power to the process electrodes;
and
(h) after (g), performing a silane soaking step comprising (1) maintaining the substrate at a second temperature of from about 100° C. to about 220° C. in the process zone comprising the pair of process electrodes, (2) introducing into the process zone, a soaking gas comprising silane, and (3) applying a second power to the process electrodes.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/978,129Filed 23 Dec 2010 · continuation
Priority: 22 Dec 2010
Published: US 2012/0164827 A128 Jun 2012
Granted: 9 Oct 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10P 70/277
During, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers: the processing being a planarisation of…
H10P 14/6336
Using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition: in the presence of a plasma [PECVD]
H10P 14/69215
Containing silicon: the material being a silicon oxide, e.g. SiO2
H10P 14/6927
The material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC: the material being a silicon…

Family

Application12/977,060Parent of this continuation · filed 22 Dec 2010
US 2012/0164827 A1Pre-grant publication · published 28 Jun 2012
US 2012/0164829 A1Published application
US 8,329,575 B2Related patent
US 8,283,237 B2This patent

From the US filing history. Foreign family members aren’t listed.