Methods of fabricating vertical channel transistors

A method of fabricating a vertical channel transistor, the method comprising:

• forming an active region on a substrate;
• forming a plurality of vertical channels by patterning the active region;
• forming a buried bit line in the active region between the vertical channels by
• removing a material of a center region of the active region to define a buried bit line pattern,
• forming a damascene bit line pattern using the buried bit line pattern, and
• forming a first conductive layer in the damascene bit line pattern;
• and
• forming a word line on a side of at least one of the vertical channels,
• wherein the forming of the buried bit line includes removing the material of the center region of the active region to form a plurality of active branches defining the buried bit line pattern, and
• the forming a plurality of vertical channels includes forming a word line pattern extending through at least one of the center region and a peripheral region of the active region to remove portions of the active branches, the vertical channels including remaining portions of the active branches.