Circuits and methods for processing memory redundancy data

A method for processing memory redundancy data, the method comprising:

• coupling serial-shift registers associated with respective redundant memory elements included in self-repairing random access memory devices on an application specific integrated circuit (ASIC) to form a redundancy chain;
• reading memory redundancy data from the serial-shift registers of the self-repairing random access memory devices of the redundancy chain;
• compressing the memory redundancy data in an interface coupled to the redundancy chain, a core logic and a test access port (TAP) on the ASIC, wherein compressing comprises a step-wise comparison of information in the memory redundancy data, the step-wise comparison responsive to an indication that a bit-slice in a particular location in the redundancy chain has been replaced by a redundant memory element;
• in a first mode of operation, storing the compressed memory redundancy data in an array of volatile memory elements in the interface coupled to the redundancy chain;
• coupling an eFuse device to the TAP;
• and
• in a second mode of operation, communicating the compressed memory redundancy data from the volatile memory elements in the interface to the eFuse device via the TAP for storage in the eFuse device;
• subsequent to the communicating, downloading the compressed memory redundancy data stored in the eFuse device by communicating the same to the interface via the TAP, storing the compressed memory redundancy data in the interface, and using the interface to decompress and shift the memory redundancy data through the serial-shift registers of the redundancy chain.