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US 8,276,149 B2Granted
Thread livelock reduction unit
AssigneeIntel Corporation
InventorsDavid W. Burns, K. S. Venkatraman
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Abstract
Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.
Claims20
A method of assigning priority among a plurality of threads in a first multi-threaded processor and a memory livelock unit, the method comprising:
- determining if among the memory livelock unit and at least two threads of the processor, the at least two threads including a first thread and a set of remaining threads, a plurality of livelock conditions are satisfied;
- determining, based on satisfaction of said plurality of livelock conditions, whether the first thread is live-locked;
- assigning priority to the first thread and not to any of the set of remaining threads in response to determining the first thread is live-locked;
- determining, based on satisfaction of said plurality of livelock conditions, whether a memory livelock reset condition is true;
- and
- assigning priority to the memory livelock unit and not to any of said at least two threads in response to determining the memory livelock reset condition is true.
3 more elements
A multithreaded processor comprising:
- a plurality of threads each having a thread livelock unit to detect livelock conditions and to monitor reset conditions;
- a memory livelock unit;
- and
- an arbitrator coupled with the plurality of threads and the memory livelock unit and based on a determination that among the memory livelock unit and at least two threads of the plurality of threads, the at least two threads including a first thread and a set of remaining threads, a plurality of livelock conditions are present, said arbitrator is to assign priority to the first thread and not to any of the set of remaining threads in response to determining that the first thread is live-locked;
- wherein
- based on a determination that said plurality of livelock conditions includes a memory livelock reset condition, the arbitrator is to assign priority to the memory livelock unit and not to any of said at least two threads in response to determining the memory livelock reset condition is true.
3 more elements
A computing system comprising:
- a system memory;
- and
- a multithreaded processor comprising:
- a cache memory to cache data from said system memory;
- a plurality of threads each having a thread livelock unit to detect livelock conditions and to monitor reset conditions;
- a memory livelock unit at least to break potential livelock conditions resulting from a long-latency cache miss;
- and
- an arbitrator coupled with the plurality of threads and the memory livelock unit and based on a determination that among the memory livelock unit and at least two threads of the plurality of threads, the at least two threads including a first thread and a set of remaining threads, a plurality of livelock conditions are present, said arbitrator is to assign priority to the first thread and not to any of the set of remaining threads in response to determining that the first thread is live-locked, wherein
- based on a determination that said plurality of livelock conditions includes a memory livelock condition, the arbitrator is to assign priority to the memory livelock unit and not to any of said at least two threads in response to determining the memory livelock condition is true.
6 more elements
Dependencies are inferred from the claim text.