Profiling of software and circuit designs utilizing data operation analyses

A computer-implemented method for modifying the configuration of a reconfigurable architecture of a hardware adaptive computing engine (ACE) in real time when ACE configuration code is executed, the adaptive computing engine having a set of one or more matrices, each matrix comprising a set of one or more computation units, each computation unit comprising a set of one or more computational elements, the method comprising:

• profiling ACE configuration code to determine a plurality of data parameters, wherein the code is executable and embodies a plurality of algorithmic elements, and wherein the code, when executed, causes a first function to be performed and a second function to be performed;
• based on the plurality of data parameters measured, selecting which of the algorithmic elements of the code are to be implemented in the reconfigurable architecture for the first function and the second function;
• reading a plurality of hardware architecture descriptions of the sets of matrices, computation units and computational elements;
• based on the hardware architecture descriptions and the selected algorithmic elements, selecting one or more computational elements;
• switching, when the ACE configuration code is executing, the interconnection network for causing the selected one or more computational elements to be connected together in a second architecture configuration for performing the second function, the switching including changing the connections among the computational elements based on the profiling to cause the computational elements to be connected in a first architecture configuration for performing the first function and cause the computational elements to be connected in a second, different architecture configuration for performing the second function.

An integrated circuit having a reconfigurable architecture, the integrated circuit being reconfigurable in real time when configuration code is executed, the integrated circuit comprising:

• a profiler for profiling configuration code to make measurements of a plurality of data parameters, wherein the code is executable to perform a first function of the code and a second function of the code and embodies a plurality of algorithmic elements
• a plurality of computational elements;
• control logic for:
• a) selecting the algorithmic elements of the code that are to be implemented in the reconfigurable architecture for the first function and the second function based on the plurality of data parameters measured,
• b) receiving a plurality of hardware architecture descriptions of the sets of matrices, computation units and computational elements, and
• c) based on the hardware architecture descriptions and the selected algorithmic elements, selecting one or more computational elements;
• and
• a reconfigurable interconnection network using real time execution of the configuration code for selectively connecting together the plurality of computational elements in a first configuration associated with the first function of the code, by switching, when the configuration code is executing, the interconnection network and causing the selected one or more computational elements to be connected together in a second architecture configuration in real time for performing the second function, the switching including changing connections among the plurality of computational elements based on the profiling to cause the plurality of computational elements to be connected in a second, different configuration for performing the second function of the code.