Reducing voltage drops in power networks using unused spaces in integrated circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDinesh Baviskar, Wen-Hao Chen, Chung-Sheng Yuan, Mark Shane Peng, Yun-Han Lee
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Abstract
A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
Claims21
A method of designing an integrated circuit, the method comprising:
- providing an integrated circuit design comprising a power network;
- providing a voltage drop mitigation system comprising a power strap enhancer configured to automatically find a source node and a terminal node in the power network;
- adding a redundant strap for the power network using the voltage drop mitigation system, wherein the redundant strap interconnects the source node and the terminal node;
- and
- after the step of adding the redundant strap, adding dummy patterns.
Dependencies are inferred from the claim text.