Mixed-height high speed reduced area cell library

A computer-based mixed-height cell library for designing a circuit, comprising:

• a computer-based first plurality of cells having a first track height;
• a computer-based second plurality of cells having a second track height and configured to be coupled to the first plurality of cells at respective power and ground rail lines;
• wherein the first and second plurality of cells are configured to be coupled at respective power and ground rail lines at a secondary layer, wherein the secondary layer is different from a primary layer, and wherein the primary layer is used to connect active material and wherein cells in adjacent rows are abutted at power rail lines or ground rail lines of adjacent rows.

The mixed-height cell library of 11, wherein the second plurality of cells of the second track height include a corresponding second set of logic functions that are equivalent in logic to the first set of logic functions and have a greater drive strength and leakage power compared to the corresponding first plurality of cells.

An integrated circuit, comprising:

• a first cell having a first track height;
• a second cell having a second track height and configured to be coupled to the first cell at respective power and ground rail lines;
• wherein the first and second cells are configured to be coupled at respective power and ground rail lines at a secondary layer, wherein the secondary layer is different from a primary layer, and wherein the primary layer is used to connect active material and wherein cells in adjacent rows are abutted at power rail lines or ground rail lines of adjacent rows.