Stress reduction on vias and yield improvement in layout design through auto generation of via fill

A non-transitory computer readable media comprising computer-executable instructions stored therein for automatic via doubling in a layout of a semiconductor device, the computer-executable instructions comprising:

• instructions to select at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers;
• instructions to select at least two metal layers of the at least one cell for via doubling;
• instructions to select metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection area comprises an existing via interconnecting the at least two metal layers;
• and
• instructions to dimensionally fit additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout, and wherein a maximum number of additional vias are fitted into each of the selected metal/metal intersection areas without changing metal layer dimensions or layout routing.

An apparatus for automatic via doubling in a layout of a semiconductor device, comprising:

• a means for selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers;
• a means for selecting at least two metal layers of the at least one cell for via doubling;
• a means for selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection area comprises an existing via interconnecting the at least two metal layers;
• and
• a means for dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout, and wherein a maximum number of additional vias are fitted into each of the selected metal/metal intersection areas without changing metal layer dimensions or layout routing.