Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications

A Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising:

• a sequence of functional units each operative to compute a corresponding term in said sequence of terms included in the error locator polynomial, each term having a degree;
• and
• a power saving unit operative to de-activate at least one individual functional unit from among said sequence of functional units, said individual functional unit being operative, when active, to compute a term whose degree exceeds said rank;
• wherein said power saving unit comprises multiple power saving logics, each power saving logic is arranged to selectively deactivate an individual subset of said functional units if all functional units in said individual subset are operative to compute terms whose degree exceeds said rank;
• wherein each subset of said functional units comprises functional units that are arranged to compute terms having degrees that form a continuous sequence of degrees.