Data writing method for a flash memory, and flash memory controller and flash memory storage apparatus using the same

A flash memory controller, for writing data from a host system into a flash memory chip, the flash memory controller comprising:

• a microprocessor unit;
• a flash memory interface unit, coupled to the microprocessor unit, and configured to couple to the flash memory chip;
• a host interface unit, coupled to the microprocessor unit and configured to couple to the host system and receive the data from the host system;
• a memory management unit, coupled to the microprocessor unit and configured to write the data into the flash memory chip;
• an error checking and correcting (ECC) unit, coupled to the microprocessor unit and configured to generating an ECC code for the data, wherein the memory management unit divides the data into at least one frame, the ECC unit generates an ECC code corresponding to the at least one frame, the memory management unit forms at least one ECC frame according to the at least one frame and the ECC code corresponding to the at least one frame, and the memory management unit divides the at least one ECC frame into a plurality of frame segments, ranks the frame segments in a non-sequentially ranking order and writes the ranked frame segments into the flash memory chip;
• and
• an error bit statistics unit, configured to determine a non-sequentially ranking order, wherein the memory management unit dividing each of a plurality of word lines of the flash memory chip into a plurality of zones, and the error bit statistics unit determines the non-sequentially ranking order for writing the frame segments into the word lines according to the number of error bits of each of the zones.

A flash memory storage apparatus, for storing data from a host system, the flash memory storage apparatus comprising:

• a connector, coupled to the host system and configured to receive the data from the host system;
• a flash memory chip;
• and
• a flash memory controller, coupled to the flash memory chip and the connector and configured to divide the data into at least one frame, generate an ECC code corresponding to the at least one frame, form at least one ECC frame according to the at least one frame and the ECC code, divide the at least one ECC frame into a plurality of frame segments, rank the frame segments in a non-sequentially ranking order and write the ranked frame segments into the flash memory chip, and configured to divide each of a plurality of word lines of the flash memory chip into a plurality of zones, the flash memory controller comprises:
• an error bit statistics unit, configured to determine the non-sequentially ranking order for writing the frame segments into the word lines according to the number of error bits of each of the zones.