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US 8,276,015 B2Granted
Managing the power-performance range of an application
AssigneeInternational Business Machines Corporation
InventorsMichael S. Floyd, Karthick Rajamani, Freeman L. Rawson, III, Malcolm S. Ware
Life of this patent
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Abstract
Semiconductor device circuits and methods are provided for adjusting core processor performance based on usage metrics. Metric detection and adjustment are performed in digital logic hardware guided by registers providing maximum and minimum frequency settings, without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Power-performance drivers provide applications or the operating system ability to specify maximum and minimum frequency requirements.
Claims15
A method for managing a power-performance range of a processor core, the method comprising:
- receiving a maximum processor frequency value and a minimum processor frequency value;
- setting the maximum processor frequency value in a first hardware register associated with a first processor core, and setting the minimum processor frequency value in a second hardware register associated with the first processor core, the first and second hardware registers operatively coupled to automatically direct power-performance control circuitry;
- executing, on the first processor core, instructions associated with a first software application;
- while executing the instructions associated with the first software application and independent of such execution, using the power-performance control circuitry to determine a processor core activity level of the first processor core, and
- control an operating frequency of the first processor core based on changes in the processor core activity level, with the power-performance control circuitry controlling the operating frequency of the first processor core to be in a range between the maximum processor frequency value and the minimum processor frequency value utilizing the first and second hardware registers;
- and
- adjusting a digital phase-locked loop circuit using the power-performance control circuitry.
4 more elements
An integrated circuit device comprising:
- a first processing circuit including a processor core, a first register, and a second register, the first register for storing an adjustable maximum frequency value for the processor core, and the second register for storing an adjustable minimum frequency value for the processor core, the processor core having an adjustable operating frequency;
- fast-adjust circuitry operatively coupled to the processor core and operable to monitor a first selected ongoing usage-level metric of the processor core,
- in response to the first selected ongoing usage-level metric having a first relationship to a determined threshold, and the minimum frequency value not already being reached, to decrease an operating frequency of the processor core, and in response to the first selected ongoing usage-level metric having a second relationship to the determined threshold, and the maximum frequency value not already being reached, to increase the operating frequency of the processor core;
- wait for a programmable time delay in response to determining the minimum frequency value has been reached or determining the maximum frequency value has been reached;
- and
- wherein operation of the fast-adjust circuitry is at least partially based on the values in the first and second registers, the first and second registers operatively coupled to automatically control the fast-adjust circuitry independently of instruction execution by the processor core.
3 more elements
An integrated circuit device comprising:
- a processor core;
- core monitoring circuit means for providing one or more digital metric output values indicating selected ongoing usage-level metrics of the processor core;
- core performance-state selection circuitry means for selecting a desired performance state from among at least two possible desired performance states, the core performance state selection circuitry means further comprising a first minimum frequency register for storing a first minimum frequency value, a second maximum frequency register for storing a second maximum frequency value, and means for automatically controlling, independently of instruction execution by the processor core, an operating frequency of the processor core to vary between the first minimum frequency value and the second maximum frequency value based on the one or more digital metric output values;
- and
- power-performance configuration driver means for detecting a change in a long-term system power-performance setting and, in response, to a change in the values in the first minimum frequency register and the second maximum frequency register.
2 more elements
Dependencies are inferred from the claim text.