Stalling synchronisation circuits in response to a late data signal

A method of processing data in data processing circuitry, said data processing circuitry comprising:

• a plurality of synchronisation circuits for capturing and transmitting said data in response to a clock signal and a plurality of combinational circuits arranged between said synchronisation circuits for processing said data, said plurality of synchronisation circuits being arranged in at least two groups of synchronisation circuits;
• said method comprising the steps of:
• determining if said data input to one of said plurality of synchronisation circuits is stable during a predetermined time and signalling an error if said data input is unstable;
• in response to said error signal:
• transmitting a control signal to at least one of said groups of synchronisation circuits that contains a subsequent synchronisation circuit that said synchronisation circuit with said unstable input is configured to transmit said data to;
• in response to receipt of said control signal:
• each of said groups of synchronisation circuits transmit a stall signal to at least one further group of synchronisation circuits that said group of synchronisation circuits is configured to transmit data to or receive data from;
• in response to receipt of said stall signal:
• said synchronisation circuits that have not stalled in a preceding clock cycle stall for a clock cycle and transmit a stall signal to said at least one further group of synchronisation circuits.

Processing means for processing data, said processing means comprising:

• a plurality of synchronisation means for capturing and transmitting said data in response to a clock signal and a plurality of combinational means arranged between said synchronisation means for processing said data, said plurality of synchronisation means being arranged in at least two groups of synchronisation means;
• an error detecting means for determining if said data input to one of said plurality of synchronisation means is stable during a predetermined time and for signalling an error if said data input is unstable, said predetermined time being less than a half cycle of said clock signal;
• control means for transmitting a stall signal to one of said groups of synchronisation means that contains a subsequent synchronisation means that said synchronisation means with said unstable input is configured to transmit said data, in response to said error detecting means signalling said error;
• said one of said groups of synchronisation means being responsive to receipt of said stall signal to stall for a clock cycle such that data is not captured or transmitted by any synchronisation means within said group during said clock cycle and to transmit said stall signal to all groups of synchronisation means that are neighbours to said group of synchronisation means, a group being a neighbour to another group if it receives data from or transmits data to said group not via any intermediate synchronisation means;
• said groups of synchronisation means being configured to respond to receipt of a stall signal from a neighbouring group to stall for a clock cycle and to transmit a stall signal to all neighbouring groups except those neighbouring groups that said stall signal has been received from.