Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value

A method of operating a microprocessor, the method comprising:

• providing a memory that is configured to store a plurality of branch information, each branch information comprising operands from a conditional branch instruction including a branch position and a jump destination, the conditional branch instruction further including a condition operand;
• pipelining, in a pipeline, a plurality of instructions for the microprocessor;
• storing a first branch information from the pipeline to the memory when a condition associated with a first conditional branch instruction is met upon execution of the first conditional branch instruction;
• and
• retrieving a second branch information from the memory to the pipeline without flushing the pipeline, when the branch position of a second branch information matches a program count value.

A system including a microprocessor, the system comprising:

• an arithmetic and logic unit (ALU);
• a plurality of registers coupled to the ALU;
• a pipeline circuit that pipelines a plurality of instructions for the microprocessor;
• a branch circuit, coupled to the pipeline circuit, that operates to store a plurality of branch information, each branch information comprising operands from a conditional branch instruction including a branch position and a jump destination, the conditional branch instruction further including a condition operand;
• and
• a control circuit, coupled to the pipeline circuit and the branch circuit, that stores a first branch information from the branch position and jump destination operands of a first conditional branch instruction to the branch circuit when condition associated with the first conditional branch instruction is met upon execution of the first conditional branch instruction, and that retrieves a second branch information from the branch circuit and loads the pipeline circuit with an instruction located at the jump destination of the second branch information when the branch position of the second branch information matches a program count value, without flushing the pipeline circuit.