# US 8,275,977 B2 · Debug signaling in a multiple processor data processing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,275,977 B2 - Document ID: US8275977B2 - Status: Granted - Kind: B2 - Application number: 12/420,521 - Filed: 2009-04-08 - Published: 2010-10-14 - Granted: 2012-09-25 - Earliest claimed: 2009-04-08 - Assignees: Freescale Semiconductor, Inc. - Inventors: William C. Moyer; Jimmy Gumulja - Web page: https://patentgrep.com/patent/US8275977B2 ## CPC - G06F 11/1679: {at clock signal level} - G06F 11/3632: {of specific synchronisation aspects} - G06F 11/1629: {Error detection by comparing the output of redundant processing systems} - G06F 11/1695: {which are operating with time diversity} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted. ## Claims ### Claim 1 A system comprising: a first processor; a second processor; a first clock coupled to the first processor; a second clock coupled to the second processor; and a third clock coupled to the first processor and to the second processor, wherein the third clock is asynchronous with respect to the first clock, wherein the first processor comprises: debug circuitry coupled to receive the third clock; synchronization circuitry coupled to receive the first clock, the synchronization circuitry receiving a first request to enter a debug mode which is synchronous with respect to the third clock and providing a first synced debug entry request signal, wherein the first synced debug entry request signal is synchronized with respect to the first clock; and an input for receiving a second synced debug entry request signal from the second processor, wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted. ### Claim 2 (depends on 1) The system of claim 1, wherein the third clock is asynchronous with respect to the first clock. ### Claim 3 (depends on 2) The system of claim 2, wherein the third clock is asynchronous with respect to the second clock. ### Claim 4 (depends on 1) The system of claim 1, wherein the debug circuitry comprises a debug request register bit, and wherein the first request to enter the debug mode is provided to the synchronization circuitry in response to the debug request register bit being asserted. ### Claim 5 (depends on 1) The system of claim 1, wherein the first processor comprises a first program counter and the second processor comprises a second program counter, and wherein the first processor increments the first program counter and the second processor increments the second program counter at a same time when both the first processor and the second processor are in the debug mode. ### Claim 6 (depends on 1) The system of claim 1, wherein the first processor and the second processor enter the debug mode and execute a same instruction in lockstep during the debug mode. ### Claim 7 (depends on 1) The system of claim 1, wherein the first processor and the second processor enter the debug mode and execute a same instruction during the debug mode, wherein execution of the same instruction by the first processor is skewed by ten or less cycles of the first clock as compared to execution of the same instruction by the second processor. ### Claim 8 (depends on 1) The system of claim 1, wherein the synchronization circuitry receives a request to exit a debug mode from the debug circuitry and provides a first synced debug exit command signal, wherein the first synced debug exit command signal is synchronized with respect to the first clock, and wherein the first processor further comprises: a first output for transferring the first synced debug entry request signal from the first processor to the second processor; a second output for transferring the first synced debug exit command signal from the first processor to the second processor; and an input for receiving a second synced debug exit command signal from the second processor, wherein the first processor waits to exit the debug mode until the first synced debug exit command signal and the second synced debug exit command signal are both asserted. ### Claim 9 (depends on 1) A system as in claim 1, wherein the second processor comprises: debug circuitry coupled to receive the third clock; synchronization circuitry coupled to receive the second clock, the synchronization circuitry receiving a second request to enter the debug mode and providing the second synced debug entry request signal to the first processor; and an input for receiving the first synced debug entry request signal from the first processor. ### Claim 10 (depends on 9) A system as in claim 9, wherein the second processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted. ### Claim 11 A method comprising: clocking a first portion of debug circuitry using a first clock; clocking a second portion of debug circuitry using a second clock, wherein the first clock is asynchronous with respect to the second clock; transferring a first request to enter a debug mode from the first portion of debug circuitry to synchronization circuitry, wherein the first request to enter the debug mode is asynchronous with respect to the second clock; a first processor synchronizing the first request to enter the debug mode with the second clock to produce a first synced debug entry request; the first processor monitoring a second synced debug entry request being received from the second processor; and the first processor waiting to enter the debug mode until the first synced debug entry request and the second synced debug entry request are both asserted. ### Claim 12 (depends on 11) A method as in claim 11, further comprising: transferring the first synced debug entry request from the first processor to a second processor. ### Claim 13 (depends on 12) A method as in claim 12, further comprising: enabling lockstep operation for the first processor and the second processor, wherein the lockstep operation comprises executing a same instruction in the first processor and the second processor during the debug mode. ### Claim 14 (depends on 11) A method as in claim 11, further comprising: transferring a request to exit a debug mode from the first portion of debug circuitry to synchronization circuitry, wherein the request to exit the debug mode is asynchronous with respect to the second clock; the first processor synchronizing the request to exit the debug mode with the second clock to produce a first synced debug exit command; the first processor monitoring a second synced debug exit command being received from the second processor; and the first processor waiting to exit the debug mode until the first synced debug exit command and the second synced debug exit command are both asserted. ### Claim 15 (depends on 12) A method as in claim 12, further comprising: the second processor synchronizing a second request to enter the debug mode with a third clock to produce the second synced debug entry request, wherein the first clock is asynchronous with respect to the third clock. ### Claim 16 (depends on 15) A method as in claim 15, wherein the second clock and the third clock are asynchronous. ### Claim 17 (depends on 15) A method as in claim 15, further comprising: before entering the debug mode, the second processor monitoring the first synced debug entry request being received from the first processor; and the second processor executing one or more instructions in the debug mode after the first synced debug entry request and the second synced debug entry request are both asserted. ### Claim 18 (depends on 11) A method as in claim 11, wherein the first processor and the second processor are formed on a same integrated circuit. ### Claim 19 A method comprising: inputting a test clock to a first processor and to a second processor; inputting a first processor clock to the first processor; inputting a second processor clock to the second processor, wherein the test clock is asynchronous with respect to the first processor clock, and wherein the test clock is asynchronous with respect to the second processor clock; the first processor receiving a first request to enter a debug mode; the second processor receiving a second request to enter the debug mode, wherein the first request to enter the debug mode and the second request to enter the debug mode are synchronous with the test clock; the first processor synchronizing the first request to enter the debug mode with respect to the first processor clock to produce a first synced debug entry request; the second processor synchronizing the second request to enter the debug mode with respect to the second processor clock to produce a second synced debug entry request; the first processor receiving the second synced debug entry request from the second processor and using the second synced debug entry request to determine when to enter debug mode; and the second processor receiving the first synced debug entry request from the first processor and using the first synced debug entry request to determine when to enter debug mode. ### Claim 20 (depends on 19) A method as in claim 19, wherein the first processor waits until both the first synced debug entry request and the second synced debug entry request are asserted before entering the debug mode, and wherein the second processor waits until both the second synced debug entry request and the first synced debug entry request are asserted before entering the debug mode.