Sequencer controlled system and method for controlling timing of operations of functional units

A sequencer controlled system for a system-on-chip (SoC) integrated circuit design, comprising:

• a plurality of functional units;
• an embedded processor operatively coupled to said plurality of functional units through a bus;
• and
• a register for controlling the start of at least one operation of said plurality of functional units with stored instructions for each of said plurality of functional units, said register further having a plurality of resources associated with numeric values which represent status information, the status information consisting of available direct memory access (DMA) transfer channels and others selected from the group consisting of processes running on said SoC, available memory area for storage, and available processing power,
• wherein the numeric values of the plurality of resources are modified based on responses received from each of the plurality of functional units,
• wherein said register sends out trigger signals concurrently, to the plurality of said hardware functional units, based on a waiting pattern programmed in said register as a direct response to being activated by said embedded processor, and keeps track of said resources based on the responses received from each of said plurality of functional units, and
• all of the resources corresponding to said waiting pattern are available before said trigger signal is sent.

A method for controlling timing of operations of functional units, said method comprising:

• configuring registers in a sequencer by an external processor to control the start of operations of functional units through a bus, said sequencer having a set of said registers;
• activating said sequencer by said external processor through said bus;
• and
• sending trigger signals to at least some of said functional units based, at least in part, upon a waiting pattern programmed in said registers,
• wherein said sequencer has a plurality of resources associated with numeric values which represent status information, the status information consisting of available direct memory access (DMA) transfer channels and others selected from the group consisting of processes, available memory area for storage, and available processing power,
• wherein the numeric values of the plurality of resources are modified based on responses received from each of the plurality of functional units,
• wherein said trigger signals are sent concurrently based on waiting patterns programmed in said registers as a direct response to being activated by said external processor and said resources are kept track of based on the responses received from each of said functional units, and
• all of the resources corresponding to said waiting pattern are available before said trigger signal is sent.