Parallel memory device rank selection
AssigneeHewlett-Packard Development Company, L.P.
InventorsLidia Warnes, Teddy Lee, Ricardo Ernesto Espinoza-Ibarra, Dennis Carr, Michael Bozich Calhoun
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Abstract
A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).
Claims10
A system comprising a translator circuit for translating a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules) by converting at least one FB-DIMM-select bit of said FB-DIMM protocol for use as a rank-select bit.
A memory access method comprising:
- issuing a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol, said memory access having at least one FB-DIMM-select bit for specifying an FB-DIMM and at least one rank-select bit specifying a rank within a selected FB-DIMM;
- converting said memory access so that at least one FB-DIMM-select bit is used with said rank-select bit to select a rank from a set of more than two ranks associated with non-fully-buffered DIMMs.
Dependencies are inferred from the claim text.