Channel tags in memory components for optimizing logical to physical address translations

A memory comprising:

• a memory array comprising physical locations;
• a translation table containing a plurality of entries mapping logical block addresses to the physical locations of the memory array;
• a translation cache to cache a subset of the plurality of entries from the translation table;
• and
• a memory controller in communication with the memory array, the translation table, and the translation cache, wherein the memory controller is configured to perform memory management functions for the memory array, including;
• receiving from a processor a read/write request including an address of a logical block and context information regarding the logical block, the context information including at least one of a relationship of the logical block to other logical blocks or a description of future activity associated with the logical block;
• and
• pre-fetching a first entry from the translation table into the translation cache based, at least in part, on the context information to optimize servicing a future read/write request associated with the read/write request.