Performance prioritization in multi-threaded processors

A processor comprising:

• a first logic to select a first subset of a plurality of cache ways to store data of threads identified as being high priority;
• a hardware thread assignment subsystem to assign a high priority thread to the first subset of the plurality of cache ways;
• and
• a second logic to reassign the high priority thread to one of the plurality of cache ways if the high priority thread remains in an inactive usage status for at least a threshold amount of time.

A computer system comprising:

• a memory to store a multi-threaded program;
• a processor core to perform the multi-threaded program;
• and
• a cache memory coupled to the processor core, wherein the cache memory includes a plurality of cache ways, a first subset of the plurality of cache ways being accessed by a high priority thread, wherein the high priority thread is reassigned to one of the plurality of cache ways if the high priority thread remains in an inactive state for at least a threshold amount of time.

An apparatus comprising:

• a processor core;
• a memory cache having a replacement policy array coupled to the processor core;
• a thread assignment mechanism coupled to the memory cache and processor core;
• and
• a cache usage monitoring system having a thread activity logic having a counter, wherein the memory cache includes a plurality of cache ways, and wherein a first subset of the plurality of cache ways is to be accessed by a high priority thread, the thread assignment mechanism to assign a lesser priority thread to a second subset of the plurality of cache ways, and the thread assignment mechanism is further to reassign the high priority thread to one of the plurality of cache ways if the high priority thread remains in an inactive usage status for at least a threshold amount of time.