Load reduction system and method for DIMM-based memory systems

A memory system which includes one or more DIMMs, each of which includes a plurality of random access memory (RAM) chips and a memory buffer circuit arranged to buffer data bytes being written to or read from said DIMM, said system nominally organized such that the bytes of a given data word are conveyed to said DIMMs via respective byte lanes and stored in a given rank consisting of parallel-connected RAM chips on a given DIMM, comprising:

• a host controller;
• a plurality of DIMM slots for receiving respective DIMMs, said host controller arranged to write data to and read data from DIMMs plugged into said slots;
• and
• wiring which provides byte lanes between said host controller and said DIMM slots via which data is written to and read from said DIMMs;
• said system arranged such that the RAM chips that constitute a given rank are re-mapped across the available DIMMs plugged into said slots such that a data word to be stored in a given rank is striped across the available DIMMs so as to reduce the loading on a given byte lane that might otherwise be present;
• wherein said host controller has m byte lanes and said system is arranged such that said re-mapping scheme requires a total of n connections between said host controller's byte lanes and said DIMM slots, further comprising a byte lane switch having m I/O ports connected to said host controller's m byte lanes and n I/O ports connected to said DIMM slots, said switch arranged to buffer data between said host controller's byte lanes and said DIMM slots such that the loading on each of said host controller's byte lanes is limited to no more than the one electrical load associated with said byte lane switch.

A method of storing data in a memory system which includes a plurality of DIMM slots adapted to receive respective DIMMs, each of which includes a plurality of random access memory (RAM) chips and a memory buffer circuit arranged to buffer and select/distribute a certain subset of data bytes being written to or read from said plurality of DIMMs, said system organized such that the bytes of a given data word are conveyed to said DIMMs via respective byte lanes that are not routed to all DIMMs and stored in a given distributed rank consisting of RAM chips on several DIMMs, comprising:

• providing a host controller;
• providing a plurality of DIMM slots for receiving respective DIMMs, said host controller arranged to write data to and read data from DIMMs plugged into said slots;
• providing wiring which provides byte lanes between said host controller and said plurality of DIMM slots via which data is written to and read from said DIMMs such that individual bytes may be read or written to RAM chips of different DIMMs as a function of said byte lane routing;
• and
• re-mapping the RAM chips that constitute a given rank across the available DIMMs plugged into said slots such that a data word to be stored in a given rank is striped across the available DIMMs so as to reduce the loading on a given byte lane that might otherwise be present.